Alternatives and similar repositories for SPICELib:

Users that are interested in SPICELib are comparing it to the libraries listed below

• paripath / cdf
  Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format
  ☆12Updated 5 years ago
• varunnagpaal / Analog-Design-Modelling
  Analog Hardware Hands on Design Labs and Modelling using SPICE Tools (NI Multisim, LTSpice)
  ☆24Updated 6 years ago
• MR-DOS / MWGEN-G1
  12.5 MHz - 6400 MHz (LMX2572) or even up to 20 GHz (LMX2595) generator board with int./ext. reference.
  ☆15Updated 3 years ago
• MorgothCreator / VerilogUtilIP
  Here is a bunch of util IPs
  ☆10Updated 6 years ago
• wsong83 / Asynchronous-Verilog-Synthesiser
  Synthesiser for Asynchronous Verilog Language
  ☆19Updated 10 years ago
• Werni2A / CadenceOSHW
  Open Source Layouts, Footprints, Schematics, Libraries, ... for Cadence Products
  ☆11Updated 2 years ago
• cbernardo / kicad_oce_vis
  experimentation with STEP/IGES visualization in kicad via OCE
  ☆13Updated 3 years ago
• mithro / valentyusb
  USB Full-Speed core written in migen/LiteX
  ☆17Updated 5 years ago
• RHSResearchLLC / xvcd
  Xilinx Virtual Cable Daemon
  ☆19Updated 5 years ago
• OpenAutomationTechnologies / VHDL_IP-Cores
  ☆16Updated 4 years ago
• tgingold / OpenTDC
  Time to Digital Converter (TDC)
  ☆30Updated 4 years ago
• myriadrf / component-libraries
  EDA component libraries
  ☆19Updated 7 years ago
• saleae / one-wire-analyzer
  Saleae 1-Wire Analyzer
  ☆11Updated last year
• medhyal / ecp5-dev-board
  ECP5 FPGA DEV BOARD
  ☆9Updated 3 years ago
• umarcor / SIEAV
  Co-simulation and behavioural verification with VHDL, C/C++ and Python/m
  ☆13Updated this week
• OpenAutomationTechnologies / openCONFIGURATOR_library
  openCONFIGURATOR 2.X core library
  ☆11Updated 6 years ago
• PeraZver / Microwave-Transmitter
  ☆11Updated 7 years ago
• goran-mahovlic / FPGA-LCD-Driver
  FPGA LVDS LCD driver
  ☆14Updated 8 years ago
• ylm / nibblecpu
  Proof of Concept to learn Amaranth as an entry effort for Supercon's RTL design competition
  ☆10Updated 2 years ago
• stnolting / cjtag_bridge
  🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.
  ☆23Updated 3 years ago
• tinyvision-ai-inc / tinyVision_sensai
  Making Lattice SensAI work properly on tinyVision products
  ☆11Updated 2 years ago
• sefffal / redpitaya-multichannelanalyser
  A fresh Multichannel Analyser app for the Red Pitaya
  ☆17Updated 7 months ago
• trabucayre / litexOnColorlightLab004
  basic example of litex on colorLight 5A-75B based on fpga_101/lab004
  ☆32Updated 2 years ago
• Qucs / gnucsator
  This package provides a gnucap based qucsator implementation.
  ☆13Updated this week
• bunnie / netv2-soc
  NeTV2 SoC based on LiteX
  ☆16Updated 6 years ago
• f32c / fpgarduino
  FPGArduino binary
  ☆13Updated 5 years ago
• freecores / mmuart
  Simple RS232 UART
  ☆12Updated 8 years ago
• warclab / dyract
  DyRACT Open Source Repository
  ☆16Updated 8 years ago
• OpenCAPI / omi_device_ice
  An example OMI Device FPGA with 2 DDR4 memory ports
  ☆16Updated 2 years ago