Alternatives and similar repositories for MIC-1-Simulator

Users that are interested in MIC-1-Simulator are comparing it to the libraries listed below

• fpgaemu / fpgaemu
  Introduction to FPGA emulation and digital design. This capstone project was part of the 2021 University of San Diego Shiley-Marcos Schoo…
  ☆54Updated 3 years ago
• zxmarcos / huedeon-gpu
  FPGA GPU design for DE1-SoC
  ☆73Updated 4 years ago
• JN513 / Risco-5
  Multi-cycle RISC-V processor with RV32I/E[M] implementation, built during a few days off.
  ☆17Updated last year
• martonbognar / vcdvis
  VCD visualizer: view your waveforms in ASCII format, or export them to TikZ figures.
  ☆32Updated 3 months ago
• pulp-platform / trdb
  RISC-V processor tracing tools and library
  ☆16Updated last year
• arm-university / Graphical-Micro-Architecture-Simulator
  Graphical-Micro-Architecture-Simulator
  ☆123Updated 7 months ago
• fpgacademy / DESim
  ☆46Updated 4 months ago
• CMU-SAFARI / DRAM-Bender
  DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art HBM…
  ☆109Updated 6 months ago
• nandland / getting-started-with-fpgas
  Verilog and VHDL for book
  ☆128Updated 2 years ago
• goossens-springer / goossens-book-ip-projects
  this repository contains all the ip projects presented in the HLS/RISC-V/Computer Architecture book written by Goossens and published by …
  ☆30Updated 5 months ago
• Domipheus / TPU
  TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. De…
  ☆150Updated 9 years ago
• jaywonchung / Verilog-Harvard-CPU
  Verilog implementation of various types of CPUs
  ☆73Updated 6 years ago
• arm-university / System-on-Chip-Design-with-Arm-Cortex-M-Processors
  A reference book on System-on-Chip Design
  ☆40Updated 7 months ago
• ahegazy / mips-cpu
  A verilog implementation of MIPS ISA.
  ☆18Updated 6 years ago
• five-embeddev / riscv-csr-access
  RISC-V CSR Access Routines
  ☆15Updated 3 years ago
• GabbedT / ApogeoRV
  A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.
  ☆20Updated 10 months ago
• yuxincs / MIPS-CPU
  A Simulative MIPS CPU running on Logisim.
  ☆140Updated 3 years ago
• Weiyet / RTLStructLib
  RTL data structure
  ☆60Updated last month
• arm-university / Modern-System-on-Chip-Design-on-Arm
  A textbook on system on chip design using Arm Cortex-A
  ☆42Updated 8 months ago
• tms4517 / 2D-Systolic-Array-Multiplier
  2D Systolic Array Multiplier
  ☆24Updated 2 years ago
• ARM-software / tarmac-trace-utilities
  Tools for analyzing and browsing Tarmac instruction traces.
  ☆81Updated 3 months ago
• PeterAaser / tdt4255-chisel-intro
  ☆26Updated 5 years ago
• dominic-meads / HDMI_FPGA
  HDMI with Verilog and an FPGA.
  ☆20Updated 2 years ago
• fcayci / vhdl-hdmi-out
  HDMI Out VHDL code for 7-series Xilinx FPGAs
  ☆63Updated 3 years ago
• Gourav0486 / AES-Core-engine-
  ☆27Updated 4 years ago
• PacktPublishing / Architecting-and-Building-High-Speed-SoCs
  Architecting and Building High Speed SoCs, published by Packt
  ☆29Updated 3 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆134Updated 4 months ago
• saursin / riscv-atom
  An open-source 32-bit RISC-V soft-core processor
  ☆45Updated 5 months ago
• leros-dev / leros
  A Tiny Processor Core
  ☆114Updated 6 months ago
• blitzingeagle / ASMBits-ARMv7
  Solutions to ASMBits ARMv7 problem set.
  ☆14Updated 8 years ago