Alternatives and similar repositories for Veecom

Users that are interested in Veecom are comparing it to the libraries listed below

• splinedrive / lets_build_a_compiler_for_riscv
  A c/RISCV of "Let's Build a Compiler" by Jack Crenshaw
  ☆114Updated 2 years ago
• rj45 / rj32
  A 16-bit RISC CPU with 32 instructions built with Digital for running on an FPGA.
  ☆124Updated 2 years ago
• x653 / xv6-riscv-fpga
  Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).
  ☆53Updated 2 years ago
• Johnlon / spam-1
  Home Brew 8 Bit CPU Hardware Implementation including a Verilog simulation, an assembler, a "C" Compiler and this repo also contains my r…
  ☆68Updated last year
• johnwinans / rvalp
  RISC-V Assembly Language Programming
  ☆237Updated last year
• franzflasch / riscv_em
  Simple risc-v emulator, able to run linux, written in C.
  ☆143Updated last year
• BrunoLevy / TinyPrograms
  Tiny programs from various sources, for testing softcores
  ☆117Updated 6 months ago
• AZHenley / riscv-parser
  Basis of a RISC-V parser to be used for linters or assemblers.
  ☆48Updated 3 years ago
• mausimus / rvcc
  Standalone C compiler for RISC-V and ARM
  ☆88Updated last year
• fmash16 / riscv_emulator
  A basic working RISCV emulator written in C
  ☆70Updated last year
• Arlet / verilog-65C02-microcode
  65C02 microprocessor in verilog, small size,reduced cycle count, asynchronous interface
  ☆73Updated 2 years ago
• michaelriri / 16-bit-risc-processor
  A 16-bit Reduced Instruction Set Computing(RISC) processor capable of fetching and executing a set of 16-bit machine instructions.
  ☆16Updated last year
• hughperkins / cpu-tutorial
  Tutorial on building your own CPU, in Verilog
  ☆34Updated 3 years ago
• lightcode / 8bit-computer
  A simple 8-bit computer build in Verilog.
  ☆64Updated 2 months ago
• popovicu / risc-v-bare-metal-fake-bios
  Code for the "fake BIOS" RISC-V example
  ☆27Updated last year
• DoctorWkt / CSCv2
  Version 2 of my Crazy Small CPU
  ☆71Updated 6 years ago
• sellicott / tcc-riscv32
  Port TCC (Tiny C Compiler) to support Risc-V 32 targets (specifically for the ESP32-C3). This project is a work-in-progress and is not cu…
  ☆69Updated last month
• mathis-s / Compiler
  From-scratch C compiler for my custom 16-bit CPU
  ☆72Updated 2 years ago
• twilco / riscv-from-scratch
  The code for the RISC-V from scratch blog post series.
  ☆93Updated 4 years ago
• michaelengel / xv6-rv32
  Port of MIT's xv6 OS to 32 bit RISC V
  ☆39Updated 3 years ago
• cr88192 / bgbtech_btsr1arch
  BtSR1 and BJX2 ISA / CPU Architecture
  ☆27Updated this week
• s-rah / pseudos
  A little risc-v assembly OS that can run DOOM on a QEMU riscv64 Virt
  ☆46Updated last year
• johnwinans / rvddt
  RISC-V Dynamic Debugging Tool
  ☆49Updated 2 years ago
• slu4coder / Minimal-UART-CPU-System
  Legacy: TTL-only CPU featuring UART I/O, an expansion port, 512KB SSD at up to 10MHz clock speed
  ☆170Updated 3 weeks ago
• noteed / riscv-hello-asm
  Bare metal RISC-V assembly hello world
  ☆58Updated 3 years ago
• smunaut / doom_riscv
  Doom classic port to lightweight RISC‑V
  ☆94Updated 3 years ago
• eddiewastaken / logisim-discrete-CPU
  An 8-Bit (mostly) discrete CPU, built in Logisim.
  ☆67Updated 2 years ago
• Arlet / verilog-6502
  A Verilog HDL model of the MOS 6502 CPU
  ☆349Updated 2 years ago
• Grubre / smol-gpu
  An rv32i inspired ISA, SIMT GPU implementation in system-verilog.
  ☆197Updated 6 months ago
• cpantel / DVGHV
  Designing Video Game Hardware in Verilog
  ☆27Updated 5 years ago