Liblor / advanced_operating_systems_2020

Related projects ⓘ

Alternatives and complementary repositories for advanced_operating_systems_2020

• ZipCPU / qoiimg
  Quite OK image compression Verilog implementation
  ☆15Updated 5 months ago
• nadavrot / bistra
  Bistra is a domain-specific language designed to generate high-performance kernels (such as GEMMs, convolutions, etc). The program is des…
  ☆6Updated 8 months ago
• regehr / pldi22-llvm-tutorial
  outline and links for PLDI 2022 tutorial
  ☆17Updated 2 years ago
• riscv / riscv-smmtt
  This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…
  ☆43Updated this week
• michalpaszkowski / LLVM-Canon
  LLVM-Canon aims to transform LLVM modules into a canonical form by reordering and renaming instructions while preserving the same semanti…
  ☆12Updated 6 months ago
• mirimmad / riscv
  RISC-V(RV32IM) emulator with support for syscalls.
  ☆25Updated last year
• Lenz-K / arm64-kvm-hello-world
  A bare metal AArch64 hello-world program, that is run in a KVM AArch64 VM.
  ☆20Updated 10 months ago
• InstLatx64 / InstLatX64_Demo
  InstLatX64_Demo
  ☆41Updated 2 weeks ago
• weirdindiankid / cacheflow
  CacheFlow is a Linux kernel module that exposes the contents of the last-level cache on *most* ARM machines.
  ☆16Updated 5 months ago
• atrosinenko / memtest86-plus-riscv
  Port of original MemTest86+ v5.1 to other architectures (RISC-V for now)
  ☆15Updated 4 years ago
• CMU-SAFARI / BEER
  BEER determines an ECC code's parity-check matrix based on the uncorrectable errors it can cause. BEER targets Hamming codes that are use…
  ☆18Updated 4 years ago
• cslab-ntua / contiguity-isca2020
  Linux source code for ISCA 2020 paper "Enhancing and Exploiting Contiguity for Fast Memory Virtualization"
  ☆17Updated 4 years ago
• pydrofoil / pydrofoil
  A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one
  ☆44Updated last month
• splinedrive / lets_build_a_compiler_for_riscv
  A c/RISCV of "Let's Build a Compiler" by Jack Crenshaw
  ☆91Updated 2 years ago
• microsoft / calipers
  Criticality-aware Framework for Modeling Computer Performance
  ☆27Updated 7 months ago
• makslevental / mmlir
  A minimal (really) out-of-tree MLIR example
  ☆34Updated 5 months ago
• IITH-Compilers / ML-Compiler-Bridge
  Library to interface Compilers and ML models for ML-Enabled Compiler Optimizations
  ☆17Updated 6 months ago
• brucehoult / rvv_example
  Simple demonstration of using the RISC-V Vector extension
  ☆37Updated 7 months ago
• eliben / c-unleashed-book-souce-code
  Source code for the "C Unleashed" book by Richard Heathfield, Lawrence Kirby, et al.
  ☆69Updated 3 years ago
• clflushopt / coldbrew
  Tracing JIT compiler and runtime for a subset of the JVM
  ☆23Updated 10 months ago
• efeslab / moesi-prime
  ☆14Updated last year
• synogate / gatery
  Gatery, a library for circuit design.
  ☆17Updated 4 months ago
• dtcxzyw / llvm-ub-aware-interpreter
  UB-aware interpreter for LLVM debugging
  ☆17Updated this week
• noteed / riscv-hello-c
  Bare metal RISC-V hello world in C
  ☆17Updated 5 years ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆27Updated 6 months ago
• geohot / tt-twitch
  tenstorrent kernel from twitch
  ☆27Updated 8 months ago
• SHTUSIST / AisLSM
  ☆10Updated 6 months ago
• mit-pdos / ward
  ☆30Updated 2 years ago
• tchajed / futex-tutorial
  ☆8Updated 3 months ago