Alternatives and similar repositories for DigitalDesignAndComputerArchitecture

Users that are interested in DigitalDesignAndComputerArchitecture are comparing it to the libraries listed below

• Azalea8 / riscv_cpu
  riscv指令集，单周期以及五级流水线CPU
  ☆101Updated 11 months ago
• PKUFlyingPig / CS61C-labs
  my implementation for the CS61C labs in 2020 summer version
  ☆83Updated 4 years ago
• shinezyy / micro-arch-training
  How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design
  ☆611Updated last year
• renyangang / riscv-mcu
  This project utilizes the Digital circuit simulation software,to build a CPU that supports a simple instruction set and simple peripheral…
  ☆74Updated 8 months ago
• xiazhuo / nscc2022_personal
  NSCSCC2022龙芯杯个人赛，MIPS32，59MHz经典五级流水线架构，易于初学者阅读（计算机组成原理，自己动手写CPU）
  ☆75Updated last year
• Tan-YiFan / DigitalLogic-Autumn2020
  复旦大学 数字逻辑与部件设计实验 2020秋
  ☆54Updated 3 years ago
• NJU-ProjectN / nvboard
  NJU Virtual Board
  ☆296Updated 3 months ago
• PKUFlyingPig / CS61C-summer20
  all the course resources of UCB's CS61C course -- Great ideas in computer architecture
  ☆342Updated 4 years ago
• ykykzq / SimpleCPU
  基于LoongArch32/MIPS32指令集的七级流水线CPU。2023年龙芯杯（NSCSCC）个人赛参赛作品。
  ☆33Updated 7 months ago
• Lyncien / RISC-V-32I
  体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
  ☆85Updated 6 years ago
• Silverster98 / bit_nscscc_suggestion
  为了更好地帮助后来的同学参加龙芯杯，草拟了这份建议，望对后来人有所帮助
  ☆133Updated 5 years ago
• lvyufeng / step_into_mips
  一步一步写MIPS CPU
  ☆843Updated 4 years ago
• OSCPU / ysyx-workbench
  ☆159Updated 2 weeks ago
• luzhixing12345 / archlab
  NUDT 高级体系结构实验
  ☆35Updated last year
• MAdrid1011 / USTC-NSCSCC
  中国科学技术大学龙芯杯参赛作品仓库合集
  ☆15Updated last year
• fluctlight001 / nscscc2022_single_tools
  龙芯杯个人赛工具包（适用于个人赛的golden_trace工具）
  ☆62Updated last year
• loongson-education / nscscc-wiki
  NSCSCC 信息整合
  ☆252Updated 4 years ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆145Updated last year
• CaptainHarryChen / StupidSysY2RV
  The final project of PKU course Compilers: Principles in Spring 2023, a SysY to RISC-V compiler. Document:：https://pku-minic.github.io/on…
  ☆21Updated 2 years ago
• Ch-EnShen / cs61c-all-materials
  This repository collects all materials from past years of cs61c.
  ☆46Updated last year
• VenciFreeman / RISC-V
  A simple RISC-V CPU written in Verilog.
  ☆68Updated last year
• 15947470421 / digital_IC_experiment
  我设计了一些数字集成电路的教学实验，供大家学习~
  ☆34Updated 10 months ago
• Zero-GGZ / FPGA-Games
  基于Xilinx Basys3的坦克大战游戏和贪吃蛇游戏
  ☆21Updated 6 years ago
• Kristoff-starling / ProjectN-CPU
  Single Cycle and Pipeline CPU of RISC-V Architecture designed for Digital Design and Computer Organization Experiments 2021, NJU
  ☆14Updated 3 years ago
• qing-2 / CPU
  单周期 8指令 MIPS32CPU
  ☆94Updated 3 years ago
• fluctlight001 / cpu_for_nscscc2022_single
  2022年龙芯杯个人赛 单发射110M（含icache）
  ☆47Updated 3 years ago
• Blue-Silence / ArchLab
  Lab for Digital Design and Computer Architecture Spring 2022 (252-0028-00L) (ETH).
  ☆15Updated 2 years ago
• viduraakalanka / HDL-Bits-Solutions
  This is a repository containing solutions to the problem statements given in HDL Bits website.
  ☆367Updated 2 years ago
• Evensgn / RISC-V-CPU
  RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
  ☆326Updated 7 years ago
• MengYueqi / HIT_CPU_verilog
  哈工大2023处理器设计与计算机体系结构实验
  ☆30Updated last year