Alternatives and similar repositories for ArchLab:

Users that are interested in ArchLab are comparing it to the libraries listed below

• OSCPU / ysyxSoC
  ☆79Updated last week
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆139Updated 4 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆49Updated 2 years ago
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆128Updated last year
• ysyx-ta / ysyx-summer-readings
  ☆61Updated 6 months ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆64Updated 3 months ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆52Updated 4 years ago
• kaitoukito / Integrated-Circuit-Textbooks
  Collect some IC textbooks for learning.
  ☆122Updated 2 years ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆181Updated 2 weeks ago
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆103Updated 2 years ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆133Updated this week
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated 8 months ago
• MrAMS / verilogModuleAddPrefix
  verilog module add prefix script 可用于ysyx项目添加学号
  ☆13Updated 11 months ago
• lauchinyuan / Booth4_wallace_MULT16_16
  A 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction
  ☆36Updated 6 months ago
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆56Updated 3 years ago
• LoveLonelyTime / Bergamot
  An exquisite superscalar RV32GC processor.
  ☆149Updated last month
• USTC-System-Courses / CECS-Lab
  ☆31Updated last year
• OSCPU / ysyx-exam
  ☆20Updated last year
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆62Updated 2 years ago
• peilin-chen / Zhulong-RISCV-CPU
  CPU Design Based on RISCV ISA
  ☆90Updated 8 months ago
• OSCPU / yosys-sta
  ☆53Updated last month
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆138Updated 2 years ago
• DawnCarol / DawnCarol
  ☆124Updated last week
• jerrylioon / Solutions-to-HDLbits-Verilog-sets
  Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).
  ☆83Updated last year
• liuqdev / 8-bits-RISC-CPU-Verilog
  Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
  ☆140Updated 6 years ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated 11 months ago
• Evensgn / RISC-V-CPU
  RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
  ☆253Updated 7 years ago
• xiaowuzxc / SparrowRV
  An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.
  ☆57Updated 2 years ago
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆130Updated 8 months ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆57Updated last year