Alternatives and similar repositories for ArchLab

Users that are interested in ArchLab are comparing it to the libraries listed below

• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆191Updated last year
• OSCPU / ysyx-workbench
  ☆159Updated 2 weeks ago
• Kristoff-starling / ProjectN-CPU
  Single Cycle and Pipeline CPU of RISC-V Architecture designed for Digital Design and Computer Organization Experiments 2021, NJU
  ☆14Updated 3 years ago
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆134Updated 2 years ago
• OSCPU / NutShell-doc
  ☆124Updated 3 years ago
• USTC-System-Courses / CECS-Lab
  ☆40Updated 2 years ago
• NJU-ProjectN / nvboard
  NJU Virtual Board
  ☆296Updated 3 months ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆165Updated this week
• ysyx-ta / ysyx-summer-readings
  ☆67Updated last year
• renyangang / riscv-mcu
  This project utilizes the Digital circuit simulation software,to build a CPU that supports a simple instruction set and simple peripheral…
  ☆74Updated 8 months ago
• MrAMS / verilogModuleAddPrefix
  verilog module add prefix script 可用于ysyx项目添加学号
  ☆13Updated last year
• MaxXSoft / Fuxi
  Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
  ☆180Updated 4 years ago
• LoveLonelyTime / Bergamot
  An exquisite superscalar RV32GC processor.
  ☆162Updated 11 months ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆217Updated last month
• Silverster98 / bit_nscscc_suggestion
  为了更好地帮助后来的同学参加龙芯杯，草拟了这份建议，望对后来人有所帮助
  ☆133Updated 5 years ago
• shinezyy / micro-arch-training
  How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design
  ☆611Updated last year
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆54Updated 3 years ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆145Updated last year
• OSCPU / ysyxSoC
  ☆89Updated 2 months ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆72Updated 2 years ago
• Evensgn / RISC-V-CPU
  RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
  ☆326Updated 7 years ago
• fluctlight001 / nscscc2022_single_tools
  龙芯杯个人赛工具包（适用于个人赛的golden_trace工具）
  ☆62Updated last year
• 15947470421 / digital_IC_experiment
  我设计了一些数字集成电路的教学实验，供大家学习~
  ☆34Updated 10 months ago
• ysyx-ta / ysyx-slides
  ☆30Updated 6 months ago
• loongson-education / nscscc-wiki
  NSCSCC 信息整合
  ☆252Updated 4 years ago
• jensen-yan / kisscpu
  国科大一生一芯第二期: RISCV-64 五级流水线CPU
  ☆18Updated 4 years ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆76Updated last month
• DawnCarol / DawnCarol
  ☆210Updated 8 months ago
• OpenXiangShan / NEMU
  Super fast RISC-V ISA emulator for XiangShan processor
  ☆302Updated this week
• xiaoan109 / ysyx-workbench
  一生一芯CPU/目前做到cache/后续主要考虑ASIC DV
  ☆22Updated 11 months ago