HDLForBeginners / HDLBits
☆9Updated 3 years ago
Alternatives and similar repositories for HDLBits:
Users that are interested in HDLBits are comparing it to the libraries listed below
- ☆93Updated last year
- Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt☆88Updated last month
- The repository for the Verilog code examples and ISE projects that accompany the book Programming FPGAs: Getting Started with Verilog.☆65Updated 7 years ago
- RISC-V CPU for OpenFPGAs, in Icestudio☆91Updated 11 months ago
- Verilog and VHDL for book☆77Updated last year
- ☆67Updated 2 years ago
- SPI Master and Slave components to be used in all of FPGAs, written in VHDL.☆36Updated 5 years ago
- Learn FPGA Programming, published by Packt☆192Updated 11 months ago
- Soft-microcontroller implementation of an ARM Cortex-M0☆25Updated 6 years ago
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆127Updated 3 years ago
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆75Updated this week
- A simple three-stage RISC-V CPU☆22Updated 4 years ago
- ☆70Updated 9 months ago
- ☆15Updated 10 months ago
- Open source ISS and logic RISC-V 32 bit project☆52Updated last week
- Example LED blinking project for your FPGA dev board of choice☆175Updated 2 months ago
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆127Updated 9 months ago
- Documenting the Lattice ECP5 bit-stream format.☆54Updated last year
- altera DE 0 Nano work☆9Updated 10 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆86Updated last week
- This repository contains the design files of RISC-V Single Cycle Core☆42Updated last year
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆45Updated last year
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆75Updated last year
- A simple 16bit system-on-chip (SoC) consisting of a CPU and GPU☆13Updated 2 weeks ago
- Simple 8-bit UART realization on Verilog HDL.☆102Updated last year
- VHDL course at Brno University of Technology☆110Updated last week
- CoreScore☆151Updated 3 months ago
- This repository contains small example designs that can be used with the open source icestorm flow.☆147Updated 3 years ago
- Projects published on controlpaths.com and hackster.io☆40Updated 2 years ago
- Architecting and Building High Speed SoCs, published by Packt☆27Updated 2 years ago