Alternatives and similar repositories for Flappy-Bird

Users that are interested in Flappy-Bird are comparing it to the libraries listed below

• PrimeMHD / FPGA_ThreeLevelStorage
  【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。
  ☆112Updated 4 years ago
• Z-Y00 / Examples-in-book-write-your-own-cpu
  《自己动手写CPU》一书附带的文件
  ☆82Updated 7 years ago
• Lyncien / RISC-V-32I
  体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
  ☆81Updated 5 years ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆135Updated 11 months ago
• name1e5s / Sirius
  Asymmetric dual issue in-order microprocessor.
  ☆34Updated 5 years ago
• Summer-Summer / ComputerArchitectureLab
  This repository is used to release the experimental assignments of Computer Architecture Course from USTC
  ☆39Updated 5 years ago
• Silverster98 / bit_nscscc_suggestion
  为了更好地帮助后来的同学参加龙芯杯，草拟了这份建议，望对后来人有所帮助
  ☆128Updated 4 years ago
• yufeiran / OpenMIPS
  实现一个基础但功能完善的计算机系统,根据《自己动手写ＣＰＵ》实现，开发板为Nexys4 DDR
  ☆33Updated last year
• z4yx / NaiveMIPS-HDL
  Naïve MIPS32 SoC implementation
  ☆115Updated 4 years ago
• Trinkle23897 / mips32-cpu
  奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）
  ☆127Updated 5 years ago
• ustb-owl / Uranus
  Uranus MIPS processor by MaxXing & USTB NSCSCC team
  ☆38Updated 5 years ago
• xupsh / Digital-Design-Lab
  ☆220Updated 4 years ago
• lllbbbyyy / FPGA-OV2640
  This project uses verilog to implement interaction with OV2640 camera, Bluetooth slave module and VGA display on FPGA.
  ☆55Updated 4 years ago
• hitwh-nscscc / simple-5stage-pipeline-MIPS-imple
  和我一步一步实现一个最简单的、带数据前推及流水线暂停的32位静态五级流水MIPS
  ☆83Updated 4 years ago
• RickyTino / MangoMIPS32
  A softcore microprocessor of MIPS32 architecture.
  ☆39Updated 11 months ago
• ruanshihai / CPU
  Verilog实现的简单五级流水线CPU，开发平台：Nexys3
  ☆40Updated 9 years ago
• loongson-education / nscscc-wiki
  NSCSCC 信息整合
  ☆242Updated 4 years ago
• zach0zhang / Single_instruction_cycle_OpenMIPS
  通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器
  ☆203Updated 3 years ago
• NSCSCC-2020-Fudan / FDU1.1-NSCSCC
  复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品
  ☆43Updated 4 years ago
• luyufan498 / CPU_start_from_0
  从零开始设计一个CPU (Verilog)
  ☆57Updated 4 years ago
• qing-2 / CPU
  单周期 8指令 MIPS32CPU
  ☆91Updated 2 years ago
• nscscc2019ucas / nscscc2019ucas
  ☆34Updated 5 years ago
• fluctlight001 / nscscc2022_single_tools
  龙芯杯个人赛工具包（适用于个人赛的golden_trace工具）
  ☆54Updated last year
• xyongcn / LoongsonCsprj2017
  Computer System Project for Loongson FPGA Board in 2017
  ☆52Updated 7 years ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆49Updated 7 months ago
• nblintao / Computer-Architecture
  A pipelined MIPS CPU supporting 31 MIPS instructions, interrupt and cache.
  ☆20Updated 9 years ago
• cxz66666 / FPGA-TankGame
  a FPGA tank game for ZJU Digital logic design
  ☆11Updated 4 years ago
• stratoes / FPGA-edge_detect
  Nexys 4 DDR Artix-7
  ☆10Updated 6 years ago
• yuxguo / USTC-ComputerArchitecture-2020S
  Code for "Computer Architecture" in 2020 Spring.
  ☆28Updated 4 years ago
• YAVGroup / Verilog-OJ
  Online judge server for Verilog | verilogoj.ustc.edu.cn
  ☆80Updated 11 months ago