BlusLiu / Flappy-Bird

Related projects ⓘ

Alternatives and complementary repositories for Flappy-Bird

• PrimeMHD / FPGA_ThreeLevelStorage
  【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。
  ☆109Updated 4 years ago
• yufeiran / OpenMIPS
  实现一个基础但功能完善的计算机系统,根据《自己动手写ＣＰＵ》实现，开发板为Nexys4 DDR
  ☆32Updated 8 months ago
• Lyncien / RISC-V-32I
  体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
  ☆65Updated 4 years ago
• Silverster98 / bit_nscscc_suggestion
  为了更好地帮助后来的同学参加龙芯杯，草拟了这份建议，望对后来人有所帮助
  ☆114Updated 4 years ago
• RickyTino / MangoMIPS32
  A softcore microprocessor of MIPS32 architecture.
  ☆39Updated 4 months ago
• name1e5s / Sirius
  Asymmetric dual issue in-order microprocessor.
  ☆34Updated 5 years ago
• NSCSCC-2020-Fudan / FDU1.1-NSCSCC
  复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品
  ☆40Updated 4 years ago
• Trinkle23897 / mips32-cpu
  奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）
  ☆126Updated 5 years ago
• z4yx / NaiveMIPS-HDL
  Naïve MIPS32 SoC implementation
  ☆113Updated 4 years ago
• cebarobot / UCAS-CALab-mycpu_verify
  计算机体系结构研讨课 2020年秋季 UCAS 《CPU 设计实战》 Lab3-Lab9
  ☆24Updated 3 years ago
• lllbbbyyy / FPGA-OV2640
  This project uses verilog to implement interaction with OV2640 camera, Bluetooth slave module and VGA display on FPGA.
  ☆55Updated 3 years ago
• nscscc2019ucas / nscscc2019ucas
  ☆33Updated 5 years ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆121Updated 4 months ago
• ustb-owl / Uranus
  Uranus MIPS processor by MaxXing & USTB NSCSCC team
  ☆38Updated 4 years ago
• ruanshihai / CPU
  Verilog实现的简单五级流水线CPU，开发平台：Nexys3
  ☆40Updated 9 years ago
• fox6666 / RISC_V-pipeline
  基于RISC_V32I指令集架构的五级流水CPU
  ☆14Updated 5 years ago
• WanQiyang / mips-cpu
  UCAS 2017秋 计算机体系结构实验 MIPS流水线CPU
  ☆8Updated 6 years ago
• nblintao / Computer-Architecture
  A pipelined MIPS CPU supporting 31 MIPS instructions, interrupt and cache.
  ☆20Updated 9 years ago
• Mionger / mp3-player
  MP3 Player developed on FPGA(DIGILENT NEXYS 4 DDR)
  ☆16Updated 5 years ago
• hitwh-nscscc / simple-5stage-pipeline-MIPS-imple
  和我一步一步实现一个最简单的、带数据前推及流水线暂停的32位静态五级流水MIPS
  ☆83Updated 4 years ago
• sailordiary / computer-systems-ucas
  中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session
  ☆30Updated 7 years ago
• loongson-education / nscscc-wiki
  NSCSCC 信息整合
  ☆220Updated 3 years ago
• xyongcn / LoongsonCsprj2017
  Computer System Project for Loongson FPGA Board in 2017
  ☆50Updated 6 years ago
• liuqdev / 8-bits-RISC-CPU-Verilog
  Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
  ☆135Updated 5 years ago
• zach0zhang / Single_instruction_cycle_OpenMIPS
  通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器
  ☆192Updated 2 years ago
• rave1sking / single_cycle_RISCV_CPU_Design-32bit
  Verilog实现单周期非流水线32位RISCV指令集（45条）CPU
  ☆35Updated 3 years ago
• Z-Y00 / Examples-in-book-write-your-own-cpu
  《自己动手写CPU》一书附带的文件
  ☆74Updated 6 years ago
• CherryYang05 / OpenMIPS_CPU
  基于龙芯 OpenMIPS 实现一个具有 89 条指令的五级流水 CPU，使用 Verilog 语言，使用哈佛结构，包括逻辑移位指令、乘除法指令、加载存储指令、转移指令、协处理器访问指令以及异常相关在内的共89条指令。能够处理数据相关，包含流水线暂停以及延迟槽
  ☆19Updated 4 years ago
• yuxguo / USTC-ComputerArchitecture-2020S
  Code for "Computer Architecture" in 2020 Spring.
  ☆29Updated 4 years ago
• YAVGroup / Verilog-OJ
  Online judge server for Verilog | verilogoj.ustc.edu.cn
  ☆77Updated 4 months ago