FPGA gaming console and crypto miner
☆13Jul 26, 2021Updated 4 years ago
Alternatives and similar repositories for copper
Users that are interested in copper are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Mining CryptoNight Haven on the Varium C1100☆10Apr 1, 2022Updated 3 years ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Feb 23, 2026Updated last month
- ☆13Feb 23, 2026Updated last month
- SQRL Port of ethminer☆11Feb 1, 2021Updated 5 years ago
- An open source FPGA miner for Blakecoin☆52Sep 22, 2014Updated 11 years ago
- A fork of Ethereum miner with OpenCL-based FPGA mining support (currently Intel FPGAs).☆43Mar 31, 2021Updated 4 years ago
- DE10 NANO SHA3-256 Proof of Work Miner☆13Sep 8, 2020Updated 5 years ago
- SHA3-256 MINER CORE☆14Aug 30, 2020Updated 5 years ago
- FPGA miner for OdoCrypt☆13Jul 25, 2019Updated 6 years ago
- Wishbone to ARM AMBA 4 AXI☆16May 25, 2019Updated 6 years ago
- Simple video chats for the web.☆47Feb 17, 2015Updated 11 years ago
- An FPGA in your USB Port☆11Jul 1, 2021Updated 4 years ago
- RISC-V 32-bit core for MCCI Catena 4710☆10Jul 31, 2019Updated 6 years ago
- RTLMeter benchmark suite☆29Mar 15, 2026Updated last week
- ☆25Aug 9, 2021Updated 4 years ago
- Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.☆12Apr 6, 2023Updated 2 years ago
- ☆21Mar 7, 2023Updated 3 years ago
- ☆28Jun 17, 2025Updated 9 months ago
- ☆21Mar 5, 2023Updated 3 years ago
- ☆11Jan 4, 2018Updated 8 years ago
- UVM Python Verification Agents Library☆15Mar 18, 2021Updated 5 years ago
- Example verilog / miner for crypto mining using AWS F1 instances☆30Jun 9, 2018Updated 7 years ago
- Some beginner projects using verilog HDL, along with some documentation on basic syntax☆13Jun 13, 2021Updated 4 years ago
- An introduction to integrated circuit design with Verilog and the Papilio Pro development board.☆15Jan 5, 2025Updated last year
- chipy hdl☆17Apr 5, 2018Updated 7 years ago
- Getting started running RISC-V Linux☆18Apr 15, 2021Updated 4 years ago
- SVA examples and demonstration☆18Sep 8, 2020Updated 5 years ago
- A set of useful mining tools to monitor your Arweave node, estimate hashrates, gather information and much more.☆31Mar 24, 2022Updated 3 years ago
- Smol 2-stage RISC-V processor in nMigen☆26May 6, 2021Updated 4 years ago
- Quick'n'dirty FuseSoC+cocotb example☆19Nov 26, 2024Updated last year
- Host software for running SSITH processors on AWS F1 FPGAs☆20Jul 20, 2021Updated 4 years ago
- RiVer Core is an open source Python based RISC-V Core Verification framework.☆23Jun 16, 2025Updated 9 months ago
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆19Mar 13, 2024Updated 2 years ago
- Python script that types out the text that exists in clipboard.☆15Mar 31, 2025Updated 11 months ago
- ☆17Feb 16, 2023Updated 3 years ago
- Implementation of go-libp2p-record in JavaScript☆16Jul 21, 2023Updated 2 years ago
- ☆12Sep 4, 2023Updated 2 years ago
- Maetti's Fork (Ethereum) + Altera/Intel OpenCL(FPGA)☆41Jan 28, 2021Updated 5 years ago
- Chia Plot Mover☆41Jan 23, 2026Updated 2 months ago