Alternatives and similar repositories for verilog_parser

Users that are interested in verilog_parser are comparing it to the libraries listed below

• amiq-consulting / amiq_blog
  Code snippets from articles published on www.amiq.com/consulting/blog
  ☆37Updated last year
• hanysalah / Design-Pattern-in-SV
  This repo is created to include illustrative examples on object oriented design pattern in SV
  ☆60Updated 2 years ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆63Updated 4 years ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆55Updated last year
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆51Updated this week
• raysalemi / fpgasimulation
  Example files for the book FPGA SIMULATION
  ☆23Updated 8 years ago
• jg-fossh / uvm-python-verification-lib
  UVM Python Verification Agents Library
  ☆15Updated 4 years ago
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆51Updated 5 years ago
• cclienti / svmodule
  SystemVerilog & Verilog Module I/O parser and printer
  ☆25Updated 4 years ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆33Updated last year
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆58Updated 6 years ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆71Updated 7 months ago
• Inkub / SV-assertions-IF-generator
  Generates a SystemVerilog assertion interface for a given SV RTL design
  ☆20Updated 10 months ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆76Updated 5 years ago
• isuckatdrifting / Gaia
  Generate UVM testbench framework template files with Python 3
  ☆27Updated 6 years ago
• sgherbst / pysvinst
  Python library for parsing module definitions and instantiations from SystemVerilog files
  ☆26Updated 4 years ago
• pulp-platform / axi_mem_if
  Simple single-port AXI memory interface
  ☆49Updated last year
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆43Updated 3 years ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆33Updated last year
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆37Updated 3 months ago
• chiggs / UVM
  Mirror of the Universal Verification Methodology from sourceforge
  ☆36Updated 11 years ago
• kaushalmodi / custom_uvm_report_server
  Customized UVM Report Server
  ☆42Updated 5 years ago
• thinkoco / systemverilog-python
  Systemverilog DPI-C call Python function
  ☆27Updated 4 years ago
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆16Updated this week
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆37Updated 8 months ago
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆41Updated 6 years ago
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆39Updated 5 years ago
• pulp-platform / axi_llc
  ☆33Updated 2 months ago
• SystemRDL / PeakRDL-uvm
  Generate UVM register model from compiled SystemRDL input
  ☆60Updated 2 months ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆75Updated last week