All code developed by the UW Orbital software team
☆24Mar 18, 2026Updated this week
Alternatives and similar repositories for orbital-software
Users that are interested in orbital-software are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ECE 350: Real-Time Operating Systems☆32Feb 11, 2026Updated last month
- This repository explores writing cocotb-style tests in modern C++, using coroutines and strong typing, with the goal of maintaining a Pyt…☆28Feb 16, 2026Updated last month
- FPGA raycaster engine written in verilog☆12Apr 19, 2019Updated 6 years ago
- A functional demo app for the Invisible Screen. Use this as a reference to build your own apps.☆22Oct 17, 2024Updated last year
- ECE 155 : Engineering Design with Embedded Systems☆14Nov 14, 2015Updated 10 years ago
- https://shallenge.quirino.net/ in zig☆25Aug 26, 2025Updated 6 months ago
- Helping you master the embedded co-op interview by explaining over 20 of the most common firmware and hardware interview questions.☆73Jan 4, 2026Updated 2 months ago
- # 3.Interview_Questions In my experience, the questions i faced in the interviews and the people surrounded me must have faced a couple o…☆25Jul 9, 2025Updated 8 months ago
- Tiny VGA Pmod board designed in KiCad☆24Sep 4, 2024Updated last year
- PCB designs for the Waterloo Aerial Robotics Group☆58Oct 8, 2025Updated 5 months ago
- Yet another RISC-V Simulator on the web, running on Webassembly! https://riscv.vercel.app/☆41May 2, 2024Updated last year
- A microcontroller-agnostic bootloader library enabling DFU capability for embedded systems☆20Jun 1, 2024Updated last year
- An editor interface for George, for SE212 at the University of Waterloo.☆27Dec 22, 2024Updated last year
- A Linked List library for C☆28Sep 25, 2020Updated 5 years ago
- A collection of commonly asked RTL design interview questions☆39May 2, 2017Updated 8 years ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆54Jan 31, 2026Updated last month
- bind-utils which includes host, dig, nslookup and nsupdate☆51Sep 8, 2015Updated 10 years ago
- Book: Quantum Computing Architecture and Hardware for Engineers - Step by Step☆149Jul 10, 2025Updated 8 months ago
- FPGA tool performance profiling☆105Feb 24, 2024Updated 2 years ago
- A command-line tool for displaying vcd waveforms.☆68Feb 19, 2024Updated 2 years ago
- ☆106Updated this week
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆140Oct 2, 2025Updated 5 months ago
- SystemVerilog frontend for Yosys☆210Updated this week
- Verilog digital signal processing components☆172Oct 30, 2022Updated 3 years ago
- OpenSTA engine☆555Mar 17, 2026Updated last week
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆176Jul 28, 2021Updated 4 years ago
- A comprehensive embedded system knowledge sharing repo that helps you ace your interviews with quick knowledge recap and interview focuse…☆701Mar 11, 2026Updated last week
- RISC-V Torture Test☆214Jul 11, 2024Updated last year
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆264Nov 6, 2024Updated last year
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆216Updated this week
- Pipeline FFT Implementation in Verilog HDL☆165Apr 14, 2019Updated 6 years ago
- SPI Slave for FPGA in Verilog and VHDL☆229May 11, 2024Updated last year
- A simple, basic, formally verified UART controller☆329Jan 29, 2024Updated 2 years ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆214Mar 17, 2026Updated last week
- Awesome ASIC design verification☆344Feb 9, 2022Updated 4 years ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆502Mar 16, 2026Updated last week
- Communication framework for RTL simulation and emulation.☆309Mar 10, 2026Updated 2 weeks ago
- The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a c…☆484Jul 18, 2025Updated 8 months ago
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,726Sep 15, 2025Updated 6 months ago