yangzebin001 / BeC---compiler
☆13Updated 3 years ago
Alternatives and similar repositories for BeC---compiler:
Users that are interested in BeC---compiler are comparing it to the libraries listed below
- 一个小型的web服务器☆10Updated 4 years ago
- JavaWeb☆17Updated 5 years ago
- A verilog parser☆18Updated 11 months ago
- symmetric clock tree synthesis for NTV IC design☆10Updated 2 years ago
- A skeleton EDA App in C++, featuring design data parsers (using Boost.Spirit), a basic GUI with Qt, a Tcl shell (with non-polling integra…☆39Updated 4 months ago
- a simple parser for verilog gate level netlist☆9Updated 9 years ago
- Library Exchange Format (LEF) and Design Exchange Format (DEF)☆19Updated 4 years ago
- A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).☆55Updated 2 years ago
- Simple Verilog Parser In Python☆15Updated 7 years ago
- Re-host of ISCAS89 sequential benchmark circuits in higher level verilog (without "DFF")☆14Updated 3 years ago
- 仓库管理系统☆15Updated 3 years ago
- Tool for parsing an integrated circuit test file from STIL to the particular file format of a Teradyne tester.☆13Updated 6 years ago
- A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).☆31Updated 9 years ago
- Design Exchange Format (DEF) parser toolkit copy. Cadence open-source parsers for DEF☆9Updated 9 years ago
- Delay Calculation ToolKit☆30Updated 2 years ago
- EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog☆25Updated 5 years ago
- Parsing library for BLIF netlists☆18Updated 5 months ago
- ☆44Updated last year
- libCircuit is a C++ Library for EDA software development☆18Updated 6 years ago
- 一个简单的使用jsp+servlet+javabean做出来的论坛网站☆18Updated 7 years ago
- liberty parser (For parsing IC timing lib file)☆54Updated last year
- A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Ve…☆25Updated 3 weeks ago
- ☆22Updated 9 months ago
- Source code for LEF/DEF☆11Updated 6 years ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆54Updated 4 years ago
- Qt实现仿QQ即时聊天程序☆228Updated 7 years ago
- Mirror of Synopsys's Liberty parser library☆20Updated 6 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆44Updated 2 months ago
- 个人QT毕业设计项目 校园商铺☆43Updated 5 years ago
- ☆12Updated 3 years ago