那部点燃啥的电视剧，不是男主C++考试用Python几行画了个爱心吗 这里“复现”了一下爱心
☆13Nov 12, 2022Updated 3 years ago
Alternatives and similar repositories for beating-heart
Users that are interested in beating-heart are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- FPGA implementation of the hector_slam algorithm using only lidar data☆10Jul 3, 2022Updated 3 years ago
- qt和常规C++项目zip压缩包解压☆10Mar 11, 2026Updated last month
- ☆16May 28, 2025Updated 11 months ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- FPGA简单入门☆12Nov 17, 2020Updated 5 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- PYNQ-T9 repo. Use antminer t9 (with 1GbE) as PYNQ devboard.☆14Nov 7, 2024Updated last year
- 爬取大众点评的店铺评论的爬虫☆18Feb 29, 2020Updated 6 years ago
- Histogram Equalization Implementation by MATLAB☆12Nov 15, 2016Updated 9 years ago
- Share video, screen, camera and audio with an RTSP stream through Lan or Wan supporting CUDA computations in a High Performance embedded …☆28Feb 19, 2020Updated 6 years ago
- Verilog HDL code and Finite State Machine (FSM) for a simple ATM☆12Jul 26, 2020Updated 5 years ago
- Design a median filter for a Generic RGB image.☆14Mar 6, 2019Updated 7 years ago
- 修改 root 用户密码及 SSH 端口一键脚本☆22Apr 3, 2024Updated 2 years ago
- 爱心树表白网页源码，jquery女神表白动画树特效☆13Sep 8, 2015Updated 10 years ago
- RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions,…☆21Nov 26, 2018Updated 7 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- c语言100道经典习题☆20Nov 12, 2019Updated 6 years ago
- SPI通信实现FLASH读写☆17Mar 18, 2020Updated 6 years ago
- verilog modules☆15May 4, 2020Updated 6 years ago
- 数字信号处理代码（matlab）☆15Nov 28, 2019Updated 6 years ago
- Yonga-MCU is a 32-bit RISCV-IMC instruction set compatible SoC design with peripherals like UART, SPI and I2C☆22Nov 21, 2022Updated 3 years ago
- python照片墙设计，将爬虫获取的照片布局成爱心形状~( Python photo wall design, layout photos taken by reptiles into a love shape~)☆12Apr 25, 2019Updated 7 years ago
- 电子科技大学2022级研究生课程《学术道德与工程伦理》，包含教材、PPT、笔记、学堂在线线上作业和小组作业。☆25Nov 26, 2022Updated 3 years ago
- UART To SPI☆19Jul 17, 2014Updated 11 years ago
- ☆38Mar 18, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆20Nov 18, 2022Updated 3 years ago
- 基于Strands agents的多智能体项目☆122Dec 26, 2025Updated 4 months ago
- Implementation of Histogram Equalization, Logarithmic Mapping, Image Rotation, Gaussian Averaging Filter and Median Filter. Histogram eq…☆17Sep 20, 2016Updated 9 years ago
- Command line tool to generate Quick Reference website.☆27Apr 21, 2026Updated 2 weeks ago
- 🐦⬛小鸦抢课: 北师大/北京师范大学/BNU/蹲课/抢课软件, 图形界面, 使用简单, 支持多线程, 跨平台😼 ！使用前请完整阅读下方使用说明！☆73Jan 8, 2026Updated 3 months ago
- 北师大计科学习攻略☆52May 28, 2025Updated 11 months ago
- Implementation of Sobel Filter in Verilog☆27Mar 10, 2017Updated 9 years ago
- Contrast Limited Adaptive Histogram Equalization☆24Mar 3, 2016Updated 10 years ago
- 电赛高频通信方向常用模块的STM32单片机驱动（基于HAL库），包括AD9910、AD9959、PE4302、SI5351，并提供详细的使用示例。☆45Aug 5, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Information and Materials for the Deep Learning Course☆31Jun 16, 2022Updated 3 years ago
- Design a custom AI inference chip. That is the goal.☆84Updated this week
- 便捷生成短视频☆32Aug 28, 2024Updated last year
- 网络渗透攻击☆53Mar 11, 2019Updated 7 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆38Oct 25, 2020Updated 5 years ago
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆40May 10, 2019Updated 6 years ago
- Asynchronous fifo in verilog☆38Mar 20, 2016Updated 10 years ago