Alternatives and similar repositories for AZPRcpu:

Users that are interested in AZPRcpu are comparing it to the libraries listed below

• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆125Updated last year
• MaxXSoft / Fuxi
  Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
  ☆166Updated 3 years ago
• OSCPU / NutShell-doc
  ☆119Updated 2 years ago
• redlightASl / Notes
  ☆65Updated this week
• OSCPU / ysyxSoC
  ☆78Updated 3 weeks ago
• jensen-yan / kisscpu
  国科大一生一芯第二期: RISCV-64 五级流水线CPU
  ☆16Updated 3 years ago
• ysyx-ta / ysyx-summer-readings
  ☆61Updated 5 months ago
• liuqdev / 8-bits-RISC-CPU-Verilog
  Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
  ☆138Updated 5 years ago
• Yawei-Ding / ysyx_riscv64_cpu
  ☆54Updated last year
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆100Updated 2 years ago
• xiaowuzxc / SparrowRV
  An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.
  ☆57Updated 2 years ago
• OSCPU / yosys-sta
  ☆49Updated 3 weeks ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆47Updated 2 years ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆37Updated last year
• TYOD-SOC / RISCV-Accelerator
  ☆36Updated 6 years ago
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆62Updated 2 years ago
• whik / e200_opensource
  The Ultra-Low Power RISC Core
  ☆47Updated 5 years ago
• CustomizableComputingLab / CustomizableComputingLab.github.io
  ☆139Updated last month
• github-3rr0r / RV32ISC
  A RISC-V RV32I ISA Single Cycle CPU
  ☆21Updated last year
• OSCPU / ysyx-workbench
  ☆125Updated 4 months ago
• myyerrol / ysyx-cpu-core
  The personal processor core of One Student One Chip project. It is a single-issue, five-stage pipelined sequential processor core based …
  ☆23Updated 3 months ago
• LoveLonelyTime / Bergamot
  An exquisite superscalar RV32GC processor.
  ☆148Updated this week
• Groupsun / riscv-mini-five-stage
  This is my graduation project, a simple processor soft core, which implements RV32I ISA.
  ☆14Updated 5 years ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆128Updated this week
• shawn110285 / Cookabarra
  a training-target implementation of rv32im, designed to be simple and easy to understand
  ☆55Updated 3 years ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆137Updated 2 years ago
• rv2036 / rv2036-website
  Official website for Jiachen Project (甲辰计划).
  ☆52Updated last month
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆133Updated 3 months ago