jianzhang96 / AZPRcpu
AZPR cpu.《CPU自制入门》附录的Verilog代码,其中的日文注释翻译成了中文。
☆36Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for AZPRcpu
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆162Updated 3 years ago
- An exquisite superscalar RV32GC processor.☆143Updated 6 months ago
- An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.☆54Updated last year
- ☆116Updated 2 years ago
- ☆76Updated 2 months ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆99Updated 2 years ago
- 一生一芯的信息发布和内容网站☆123Updated last year
- ☆119Updated 2 months ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆116Updated last month
- ☆43Updated 4 months ago
- ☆178Updated last year
- ☆65Updated last week
- 《从零开始的RISC-V模拟器开发》配套的PPT和教学资料☆194Updated 3 years ago
- ☆52Updated last year
- ☆35Updated 6 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆46Updated 2 years ago
- a training-target implementation of rv32im, designed to be simple and easy to understand☆55Updated 2 years ago
- The Ultra-Low Power RISC Core☆47Updated 5 years ago
- ☆60Updated 3 months ago
- ☆102Updated last year
- This is a repo for recording and reporting RISCV platform's test and measurement continuously.☆53Updated 11 months ago
- ☆16Updated last year
- Modern co-simulation framework for RISC-V CPUs☆118Updated this week
- ☆137Updated 2 weeks ago
- ☆32Updated last year
- NJU Virtual Board☆236Updated 3 months ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆36Updated last year
- verilog module add prefix script 可用于ysyx项目添加学号☆13Updated 8 months ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆107Updated 2 years ago