Alternatives and similar repositories for AZPRcpu

Users that are interested in AZPRcpu are comparing it to the libraries listed below

• MaxXSoft / Fuxi
  Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
  ☆179Updated 4 years ago
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆135Updated 2 years ago
• OSCPU / NutShell-doc
  ☆124Updated 3 years ago
• lmxyy / Computer-Architecture-Task-2
  Riscv32 CPU Project
  ☆94Updated 7 years ago
• OSCPU / ysyx-workbench
  ☆157Updated 3 weeks ago
• LoveLonelyTime / Bergamot
  An exquisite superscalar RV32GC processor.
  ☆162Updated 10 months ago
• runninglinuxkernel / riscv_programming_practice
  ☆222Updated 2 years ago
• NJU-ProjectN / nvboard
  NJU Virtual Board
  ☆294Updated 2 months ago
• Edragon / FPGA_DOCS
  ☆138Updated 6 years ago
• OpenXiangShan / NEMU
  Super fast RISC-V ISA emulator for XiangShan processor
  ☆300Updated last week
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆186Updated last year
• USTC-System-Courses / CECS-Lab
  ☆40Updated 2 years ago
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆66Updated 3 years ago
• redlightASl / Notes
  ☆86Updated 2 weeks ago
• rv2036 / rv2036-website
  Official website for Jiachen Project (甲辰计划).
  ☆61Updated last month
• liuqdev / 8-bits-RISC-CPU-Verilog
  Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。
  ☆153Updated 6 years ago
• hehao98 / RISCV-Simulator
  A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation
  ☆197Updated last year
• NJU-ProjectN / fceux-am
  ☆101Updated last week
• luzhixing12345 / archlab
  NUDT 高级体系结构实验
  ☆35Updated last year
• zach0zhang / Single_instruction_cycle_OpenMIPS
  通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器
  ☆206Updated 3 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆53Updated 3 years ago
• plctlab / writing-your-first-riscv-simulator
  《从零开始的RISC-V模拟器开发》配套的PPT和教学资料
  ☆232Updated 4 years ago
• xiaowuzxc / SparrowRV
  An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.
  ☆71Updated 2 years ago
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆32Updated 3 years ago
• ysyx-ta / ysyx-summer-readings
  ☆67Updated last year
• VenciFreeman / RISC-V
  A simple RISC-V CPU written in Verilog.
  ☆67Updated last year
• ISRC-CAS / riscv-isa-manual-cn
  ☆206Updated last month
• CherrySprings / CherrySprings
  ☆19Updated 2 years ago
• jensen-yan / kisscpu
  国科大一生一芯第二期: RISCV-64 五级流水线CPU
  ☆18Updated 4 years ago
• renyangang / riscv-mcu
  This project utilizes the Digital circuit simulation software,to build a CPU that supports a simple instruction set and simple peripheral…
  ☆71Updated 7 months ago