Miscellanious projects during 2014-2018 in Dept. of Electronic Engineering, Tsinghua University
☆27Mar 29, 2019Updated 7 years ago
Alternatives and similar repositories for THUEE-course-misc
Users that are interested in THUEE-course-misc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Config files for my GitHub profile.☆11Updated this week
- a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.☆11Dec 14, 2019Updated 6 years ago
- ☆11Dec 1, 2023Updated 2 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- DDR4 Simulation Project in System Verilog☆47Aug 18, 2014Updated 11 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- learn to allocate wireless resources with GNN in over-the-air FL system☆10Jun 4, 2023Updated 3 years ago
- Modeling Harmonic Complexity using two models of Conditional Variational Autoencoders - MSc. Thesis☆10May 16, 2023Updated 3 years ago
- Parallel_Computer_Architecture经典书籍☆17May 13, 2022Updated 4 years ago
- IEEE VCIP 2021: AnomalyHop: An SSL-based Image Anomaly Localization Method☆14Sep 18, 2021Updated 4 years ago
- About Us☆19Mar 30, 2024Updated 2 years ago
- YSYX RISC-V Project NJU Study Group☆16Jan 3, 2025Updated last year
- Time-domain Audio Separation Network☆24Aug 3, 2018Updated 7 years ago
- Readme☆14Mar 15, 2026Updated 4 months ago
- P4_16 reference compiler☆23Dec 30, 2025Updated 6 months ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- A Flexible Cache Architectural Simulator☆17Sep 16, 2025Updated 10 months ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- 计算机组织与设计硬件软件接口 原书与伯克利大学哔哩哔哩视频课件☆22May 13, 2022Updated 4 years ago
- Uses the D8M camera module, then processes the image to detect red objects, and then overlay an x,y crosshair on the largest red object. …☆15Jan 19, 2018Updated 8 years ago
- The TV80 (Verilog) synthesizable soft core of Zilog Z80 (forked from http://opencores.org/project,tv80)☆10Jan 9, 2016Updated 10 years ago
- DCASE2016 TASK1 Scene Classification☆12May 2, 2017Updated 9 years ago
- ☆14Oct 24, 2025Updated 9 months ago
- Source Code for the ICML Paper "Curriculum Reinforcement Learning via Constrained Optimal Transport"☆16Jun 9, 2022Updated 4 years ago
- This repository collects papers related to Speech Tokenizer.☆18Oct 16, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- This is Max's blog, something interesting in it.☆13Jan 1, 2023Updated 3 years ago
- Implementation of Partially Parellel LDPC Code Decoder in Verilog☆15Jul 23, 2020Updated 6 years ago
- Joker TV (USB) FPGA verilog/vhdl code☆16May 19, 2026Updated 2 months ago
- A basic documentation generator for Verilog, similar to Doxygen.☆13Aug 5, 2016Updated 9 years ago
- Meta-learning model agnostic (MAML) implementation for cross-accented ASR☆45Feb 9, 2024Updated 2 years ago
- Zedboard projects☆11May 15, 2016Updated 10 years ago
- This is a simple VLIW based processor written in Verilog. A Python script has also been included to simulate static instruction schedulin…☆18May 14, 2021Updated 5 years ago
- A graph-based deep MIDI music generator. Official repository of the paper "Graph-based Polyphonic Multitrack Music Generation".☆21Oct 13, 2023Updated 2 years ago
- ☆22Mar 30, 2024Updated 2 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Integrated Circuit Design Laboratory(IC Lab) at 2019 Fall, NCTU. Final project is a customized 16 bits ISA processor.☆24Sep 21, 2021Updated 4 years ago
- ☆12Jan 19, 2022Updated 4 years ago
- ☆13Aug 12, 2024Updated last year
- 2020年的白皮书，报告等☆19Jan 4, 2021Updated 5 years ago
- The hardware implementation of Poseidon hash function in SpinalHDL☆21Jun 5, 2022Updated 4 years ago
- ☆17Jul 21, 2017Updated 9 years ago
- Image Signal Processing Assignments☆16May 1, 2018Updated 8 years ago