Alternatives and similar repositories for LectureNotes

Users that are interested in LectureNotes are comparing it to the libraries listed below

• EDDI-WebAppAcademy / Documents
  소프트웨어 설치와 관련한 기본적인 설정 문서들
  ☆20Updated 3 years ago
• EDDI-RobotAcademy / WebAppPersonalProject
  웹/앱 과정 개인 프로젝트
  ☆19Updated 2 years ago
• EDDI-RobotAcademy / SDC-AI-LectureNotes
  It's for SDC-AI Lecture Notes
  ☆15Updated last year
• KHWeb19 / LectureContents
  수업 자료는 모두 여기에 업로드 됩니다.
  ☆26Updated 3 years ago
• KHWeb19 / Homework
  과제는 여기에 제출합니다.
  ☆25Updated 3 years ago
• EDDI-RobotAcademy / supplement-lecture
  웹/앱 보충 강의
  ☆13Updated 2 years ago
• EDDI-RobotAcademy / Vue-Basics
  Vue Basics
  ☆10Updated 2 years ago
• Xilinx / DPU-PYNQ
  DPU on PYNQ
  ☆241Updated 5 months ago
• roo16kie / MAC_Verilog
  Using verilog to implement MAC (Multiply Accumulate) . Verifying it by testbench .
  ☆14Updated 6 years ago
• gewuek / vitis_ai_custom_platform_flow
  This project is trying to create a base vitis platform to run with DPU
  ☆49Updated 5 years ago
• Avnet / Ultra96-PYNQ
  Board files to build Ultra 96 PYNQ image
  ☆157Updated 4 months ago
• definelicht / hlslib
  A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
  ☆334Updated last year
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆124Updated 11 years ago
• Xilinx / XilinxBoardStore
  ☆312Updated this week
• amiq-consulting / CNN-using-HLS
  Convolutional Neural Network Using High Level Synthesis
  ☆90Updated 5 years ago
• Xilinx / DSP-PYNQ
  A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+
  ☆40Updated 3 years ago
• xupgit / Zynq-Design-using-Vivado
  This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.
  ☆86Updated 2 years ago
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆107Updated 7 years ago
• Jefferson-Lopes / FFT
  FFT algorithm for fpga
  ☆25Updated 4 years ago
• thedatabusdotio / fpga-ml-accelerator
  This repository hosts the code for an FPGA based accelerator for convolutional neural networks
  ☆180Updated last year
• xupgit / Embedded-System-Design-Flow-on-Zynq
  Updated version of the XUP Workshops
  ☆12Updated 7 years ago
• keyonhome / AXI4_LiteIP
  A verilog FPGA Interface for AXI4_Lite from Slave side
  ☆11Updated 5 years ago
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆163Updated 3 years ago
• AniketBadhan / Convolutional-Neural-Network
  Implementation of CNN using Verilog
  ☆238Updated 8 years ago
• Xilinx / finn-hlslib
  Vitis HLS Library for FINN
  ☆213Updated 3 weeks ago
• xupgit / FPGA-Design-Flow-using-Vivado
  This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite
  ☆102Updated 6 years ago
• Xilinx / PYNQ-HelloWorld
  This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.
  ☆107Updated 3 years ago
• boaaaang / CNN-Implementation-in-Verilog
  Convolutional Neural Network RTL-level Design
  ☆74Updated 4 years ago
• djtfoo / lenet5-verilog
  A Verilog design of LeNet-5, a Convolutional Neural Network architecture
  ☆34Updated 5 years ago
• StefanSredojevic / Deep-Neural-Network-Hardware-Accelerator
  SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…
  ☆112Updated 5 years ago