Alternatives and similar repositories for Nexys-4-DDR-Keyboard:

Users that are interested in Nexys-4-DDR-Keyboard are comparing it to the libraries listed below

• z4yx / NaiveMIPS-HDL
  Naïve MIPS32 SoC implementation
  ☆113Updated 4 years ago
• PrimeMHD / FPGA_ThreeLevelStorage
  【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。
  ☆110Updated 4 years ago
• name1e5s / Sirius
  Asymmetric dual issue in-order microprocessor.
  ☆34Updated 5 years ago
• RickyTino / MangoMIPS32
  A softcore microprocessor of MIPS32 architecture.
  ☆39Updated 7 months ago
• NSCSCC-2020-Fudan / FDU1.1-NSCSCC
  复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品
  ☆41Updated 4 years ago
• Silverster98 / bit_nscscc_suggestion
  为了更好地帮助后来的同学参加龙芯杯，草拟了这份建议，望对后来人有所帮助
  ☆118Updated 4 years ago
• thu-cs-lab / supervisor-rv
  计算机组成原理课程 RISC-V 监控程序，支持 32 位和 64 位
  ☆114Updated 5 months ago
• YAVGroup / Verilog-OJ
  Online judge server for Verilog | verilogoj.ustc.edu.cn
  ☆77Updated 7 months ago
• ustb-owl / Uranus
  Uranus MIPS processor by MaxXing & USTB NSCSCC team
  ☆38Updated 5 years ago
• ZJUArch / verilog-general-guide
  ☆18Updated 7 years ago
• sxtyzhangzk / mips-cpu
  A MIPS CPU implemented in Verilog
  ☆66Updated 7 years ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆122Updated 7 months ago
• YanB25 / Tomasulo
  An out-of-order execution algorithm for pipeline CPU, implemented by verilog
  ☆39Updated 6 years ago
• Lyncien / RISC-V-32I
  体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
  ☆72Updated 5 years ago
• zencove-thu / zencove-zoom
  Highly configurable out-of-order MIPS32 processor, capable of booting Linux.
  ☆38Updated last year
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆46Updated last year
• Trinkle23897 / mips32-cpu
  奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）
  ☆126Updated 5 years ago
• bit-mips / cpu
  MIPS CPU
  ☆14Updated 4 years ago
• MaxXSoft / Fuxi
  Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
  ☆168Updated 3 years ago
• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆74Updated last year
• trivialmips / TrivialMIPS
  MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
  ☆105Updated 5 years ago
• huang-jl / LLCL-MIPS
  LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…
  ☆34Updated 3 years ago
• iBug / backTCP-python
  backTCP is a course lab of « Computer Networking » in fall 2019 of USTC
  ☆17Updated 5 years ago
• Z-Y00 / Examples-in-book-write-your-own-cpu
  《自己动手写CPU》一书附带的文件
  ☆78Updated 6 years ago
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆128Updated last year
• loongson-education / nscscc-wiki
  NSCSCC 信息整合
  ☆229Updated 3 years ago
• yufeiran / OpenMIPS
  实现一个基础但功能完善的计算机系统,根据《自己动手写ＣＰＵ》实现，开发板为Nexys4 DDR
  ☆33Updated 11 months ago
• hitwh-nscscc / simple-5stage-pipeline-MIPS-imple
  和我一步一步实现一个最简单的、带数据前推及流水线暂停的32位静态五级流水MIPS
  ☆83Updated 4 years ago
• xyongcn / LoongsonCsprj2017
  Computer System Project for Loongson FPGA Board in 2017
  ☆52Updated 6 years ago
• sailordiary / computer-systems-ucas
  中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session
  ☆30Updated 7 years ago