Alternatives and similar repositories for CXLPapers

Users that are interested in CXLPapers are comparing it to the libraries listed below

• SlugLab / CXLMemSim
  CXLMemSim: A pure software simulated CXL.mem for performance characterization
  ☆161Updated 3 weeks ago
• spypaul / MQSim_CXL
  ☆71Updated 2 years ago
• MoatLab / Pond
  Pond: CXL-Based Memory Pooling Systems for Cloud Platforms (ASPLOS'23)
  ☆203Updated 8 months ago
• cosmoss-jigu / memtis
  Tiered memory management
  ☆78Updated 10 months ago
• cxl-reskit / cxl-reskit
  CXL Memory Resource Kit top-level repository
  ☆55Updated 2 years ago
• ece-fast-lab / cxl_type3_tests
  This is the respository that holds the artifacts of MICRO'23 -- Demystifying CXL Memory with True CXL-Ready Systems and CXL Memory Device…
  ☆48Updated last year
• thustorage / TeRM
  TeRM: Extending RDMA-Attached Memory with SSD [FAST'24]
  ☆44Updated 8 months ago
• madsys-dev / sosp-paper19-ae
  The Artifact Evaluation Version of SOSP Paper #19
  ☆48Updated 10 months ago
• spypaul / MQSim_CXL_Linux
  ☆26Updated 2 years ago
• ferry-hhh / CXL-DMSim
  CXL-DMSim: A Full-System CXL Disaggregated Memory Simulator Based on gem5
  ☆78Updated 3 months ago
• zxhero / gem5-CXL
  This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…
  ☆36Updated 11 months ago
• lingfenghsiang / Nomad
  OSDI'24 Nomad implementation
  ☆45Updated 7 months ago
• twicy / awesome-CXL
  This is a repo listing papers/blogs/news related to CXL. Let's take the leap to Next-Gen memory system with the awesome CXL
  ☆17Updated last year
• project-kona / asplos21-ae
  ☆30Updated 4 years ago
• dmemsys / awesome-disaggregated-memory
  A collection of awesome researchers and papers about disaggregated memory.
  ☆158Updated 3 weeks ago
• host-architecture / colloid
  Tiered Memory Management: Access Latency is the Key!
  ☆50Updated 3 months ago
• cloudarxiv / emucxl
  ☆14Updated 10 months ago
• bytedance / eurosys24-artifacts
  Artifacts of EuroSys'24 paper "Exploring Performance and Cost Optimization with ASIC-Based CXL Memory"
  ☆27Updated last year
• thustorage / lambda-io
  λ-IO: a unified I/O stack for computational storage [FAST'23]
  ☆76Updated 2 months ago
• clusterfarmem / fastswap
  Fastswap, a fast swap system for far memory through RDMA
  ☆80Updated last year
• PDS-Lab / Rcmp
  Rcmp: Reconstructing RDMA-based Memory Disaggregation via CXL
  ☆56Updated last year
• ysarch-lab / nimble_page_management_asplos_2019
  Kernel repo of "Nimble Page Management for Tiered Memory Systems" in ASPLOS 2019
  ☆44Updated 2 years ago
• Sys-KU / AutoTiering
  [USENIX ATC '21] Exploring the Design Space of Page Management for Multi-Tiered Memory Systems
  ☆47Updated 3 years ago
• WukLab / Clio
  Clio, ASPLOS'22.
  ☆77Updated 3 years ago
• CMU-SAFARI / Sibyl
  Source code for the software implementation of Sibyl proposed in our ISCA 2022 paper: Gagandeep Singh et. al., "Sibyl: Adaptive and Exten…
  ☆36Updated 2 years ago
• SimpleSSD / SimpleSSD-FullSystem
  Open-Source Licensed Educational SSD Simulator for High-Performance Storage and Full-System Evaluations
  ☆105Updated 5 years ago
• OpenMPDK / SMDK
  SMDK, Scalable Memory Development Kit, is developed for Samsung CXL(Compute Express Link) Memory Expander to enable full-stack Software-D…
  ☆293Updated 7 months ago
• spcl / CoRM
  CoRM: Compactable Remote Memory over RDMA
  ☆20Updated 4 years ago
• cyjseagull / gem5-nvmain-hybrid-simulator
  gem5-nvmain hybrid simulator supporting simulation of DRAM-NVM hybrid memory system
  ☆77Updated 5 years ago
• sylab / multi-clock
  Sources for the Multi-Clock system as described in the paper: MULTI-CLOCK: Dynamic Tiering for Hybrid Memory Systems, HPCA 2022.
  ☆19Updated 3 years ago