sean-chester / exploiting-modern-hardwareView external linksLinks
CSC 485C/586C @ UVic: Data Management on Modern Hardware. Teaches techniques to expose and exploit parallelism on superscalar/multicore/gpu architectures.
☆15Mar 31, 2021Updated 4 years ago
Alternatives and similar repositories for exploiting-modern-hardware
Users that are interested in exploiting-modern-hardware are comparing it to the libraries listed below
Sorting:
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Updated this week
- ☆12Aug 12, 2022Updated 3 years ago
- 学习java过程中产生的代码，主要是java编程思想中的练习☆10Oct 13, 2017Updated 8 years ago
- ☆37Dec 10, 2020Updated 5 years ago
- Experiments with k-wave.org and octave☆10Aug 16, 2015Updated 10 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- Simulator for a superscalar processor with dynamic scheduling and branch prediction☆15Nov 23, 2018Updated 7 years ago
- 经典的嵌入式OS - ucos-II 2.52版本全注释，仅供学习交流使用。☆12Oct 16, 2019Updated 6 years ago
- Do not run this, if you love your pc.☆11Dec 2, 2020Updated 5 years ago
- Ticket system☆118Feb 27, 2014Updated 11 years ago
- 3D BIM Viewer; BIMsurfer extended☆10Oct 8, 2012Updated 13 years ago
- FPGA Labs for EECS 151/251A (Fall 2021)☆11Oct 20, 2021Updated 4 years ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆21Apr 25, 2025Updated 9 months ago
- RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga☆14Feb 26, 2025Updated 11 months ago
- Running ahead of memory latency - Part II project☆10Jan 7, 2023Updated 3 years ago
- Update an ECS service to use a new Docker image☆13Updated this week
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆20Nov 9, 2025Updated 3 months ago
- ExaWorks SDK☆11Feb 1, 2024Updated 2 years ago
- simple 4-BIT CPU with 74-serials chip，origin by Kaoru Tonami in his book “How to build a CPU”☆14Oct 19, 2024Updated last year
- Local package cache as first class citizen.☆12Jan 6, 2023Updated 3 years ago
- Works for Applied Deep Learning / Machine Learning and Having It Deep and Structured (2017 FALL) @ NTU☆11Aug 14, 2018Updated 7 years ago
- Explore the behavior SystemC kernel event-driven simulator (aka "the engine")☆11Jan 17, 2024Updated 2 years ago
- livecoding talk for oscon 2018☆10Jul 18, 2018Updated 7 years ago
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- A Flexible Cache Architectural Simulator☆16Sep 16, 2025Updated 5 months ago
- Linux porting to NonTrivialMIPS (based on linux-stable)☆12Aug 17, 2019Updated 6 years ago
- WeBankBlockchain-Data数据治理通用组件文档☆14Mar 1, 2023Updated 2 years ago
- A docker image for One Student One Chip's debug exam☆10Sep 22, 2023Updated 2 years ago
- ☆13May 8, 2025Updated 9 months ago
- ☆16Jan 18, 2025Updated last year
- CATIA CAA V5 Training Code, Projects backup, etc..☆12May 10, 2022Updated 3 years ago
- HeliosXCore is a Superscalar Out-of-order RISC-V Processor Core.☆10Mar 8, 2024Updated last year
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆24Updated this week
- ☆15Dec 17, 2025Updated last month
- Sifive All Aboard 系列文章翻译☆11Nov 26, 2021Updated 4 years ago
- Vivado in GitLab-Runner for GitLab CI/CD☆10Oct 27, 2022Updated 3 years ago
- A virtio layer for xv6☆12Apr 16, 2019Updated 6 years ago
- Digital system design: Training lessons and exercise projects for students☆11May 12, 2023Updated 2 years ago
- Deep learning algorithms developed by ourselves from scratch by C++. No deep learning frameworks are used.☆10Aug 3, 2020Updated 5 years ago