Alternatives and similar repositories for sublime-spice:

Users that are interested in sublime-spice are comparing it to the libraries listed below

• devbisme / myhdl-resources
  A collection of awesome MyHDL tutorials, projects and third-party tools.
  ☆93Updated 3 years ago
• PyFPGA / pyfpga
  A Python package to use FPGA development tools programmatically.
  ☆96Updated last month
• intel / multi_power_sequencer
  Multi-Rail Power Sequencer, capable of monitoring and sequencing up to 144 power rails, offers a configurable and rich set of features, s…
  ☆17Updated last month
• hadipourh / AES-VHDL
  VHDL Implementation of AES Algorithm
  ☆75Updated 3 years ago
• cfelton / rhea
  A collection of MyHDL cores and tools for complex digital circuit design
  ☆85Updated 6 years ago
• Lenty / SLiCAP_python
  Open-source version of SLiCAP, implemented in python
  ☆35Updated last month
• Digilent / Zybo-Z7-20-pcam-5c
  ☆54Updated 2 years ago
• acidbourbon / numpy_ltspice_filter
  A python module for seamless integration of analog filters designed in LTspice into Python3/Numpy signal processing projects.
  ☆49Updated 2 months ago
• parallella / openeda
  Open source EDA chip design flow
  ☆49Updated 7 years ago
• FMCHUB / Lib_Altium
  Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard
  ☆42Updated 3 years ago
• imrickysu / ZYNQ-Custom-Board-Bring-Up-Guide
  This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project th…
  ☆64Updated 7 years ago
• Digilent / Petalinux-Zybo
  ☆26Updated 6 years ago
• ggventurini / python-deltasigma
  A port of the MATLAB Delta Sigma Toolbox based on free software and very little sleep
  ☆87Updated 2 years ago
• mvsoliveira / IBERTpy
  A Python package for running IBERT Eye scan in Vivado, ploting eye diagrams with mathplotlib and compiling results with LaTeX
  ☆12Updated 3 years ago
• Digilent / digilent-vivado-scripts
  ☆64Updated 6 months ago
• devbisme / pygmyhdl
  MyHDL hardware design language encased in the tasty PygMyHDL wrapper.
  ☆19Updated 2 years ago
• PyHDI / PyCoRAM
  Python-based Portable IP-core Synthesis Framework for FPGA-based Computing
  ☆52Updated 8 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆55Updated last year
• hgomersall / Ovenbird
  A tool for merging the MyHDL workflow with Vivado
  ☆19Updated 4 years ago
• Avnet / hdl
  ☆107Updated last month
• wavedrom / cli
  CLI for WaveDrom
  ☆61Updated 10 months ago
• ignamv / ngspyce
  Python bindings for ngspice simulation engine
  ☆66Updated 4 years ago
• robseb / rsyocto
  🤖 SoCFPGA: Open-Source Embedded Linux Distribution with a highly flexible build system, developed for Intel (ALTERA) SoC-FPGAs (Cyclone …
  ☆103Updated 3 years ago
• byuccl / spydrnet
  A flexible framework for analyzing and transforming FPGA netlists. Official repository.
  ☆92Updated 10 months ago
• MauererM / VIIRF
  Hardware description (VHDL) and configuration scripts (Python) of a versatile IIR Filter implemented as cascaded SOS/biquads. No vendor-s…
  ☆19Updated 6 years ago
• Schweitzer-Engineering-Laboratories / fixedpoint
  Fixed point arithmetic python package
  ☆36Updated last year
• Isotel / mixedsim
  Hardware Design Tool - Mixed Signal Simulation with Verilog
  ☆76Updated last month
• rwpenney / spfpm
  Package for performing fixed-point, arbitrary-precision arithmetic in Python.
  ☆64Updated 10 months ago
• ZipCPU / dspfilters
  A collection of demonstration digital filters
  ☆142Updated last year
• benreynwar / pyvivado
  Python tools for Vivado Projects
  ☆73Updated 5 years ago