CNES Edition of the VHDL Rules
☆11Oct 20, 2021Updated 4 years ago
Alternatives and similar repositories for VHDL_Handbook_CNE
Users that are interested in VHDL_Handbook_CNE are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An 8b10b decoder and encoder in logic in VHDL☆28Apr 12, 2021Updated 5 years ago
- Multi-function, universal, fixed-point CORDIC☆16Feb 20, 2022Updated 4 years ago
- ☆15May 29, 2020Updated 6 years ago
- sonar-hadolint-plugin is a SonarQube plugin used to integrate Hadolint results☆13Apr 26, 2023Updated 3 years ago
- Tester for IS61WV5128BLL-10BLI SRAM in Cmod A7-35T☆20Nov 25, 2018Updated 7 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- 1G eth UDP / IP Stack☆10Jul 17, 2014Updated 12 years ago
- Docker version of SonarQube with preconfigured plugins and settings dedicated to Continuous Integration.☆12Feb 13, 2026Updated 8 months ago
- ☆16Oct 5, 2026Updated last week
- Docker container for running a Space Engineers server on Linux.☆11Nov 14, 2015Updated 10 years ago
- ARTICo³ - Dynamic and Partially Reconfigurable Architecture for Run-Time Adaptive, High Performance Embedded Computing☆12Oct 1, 2026Updated 2 weeks ago
- ☆24Oct 23, 2020Updated 5 years ago
- uvm_starter is a simple template for starting uvm projects☆12Feb 11, 2025Updated last year
- Dockerized FPGA toolchains containing openxc7, f4pga, vivado and more☆18Sep 12, 2026Updated last month
- Add capability to analyze Fortran in SonarQube through i-Code CNES.☆21Sep 26, 2025Updated last year
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Docker image for cppcheck☆20Sep 26, 2026Updated 3 weeks ago
- ☆12Mar 1, 2021Updated 5 years ago
- SonarQube plugin for Puppet code.☆26May 22, 2019Updated 7 years ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Jan 30, 2025Updated last year
- A multi-threaded microprocessor interleaving as minimum three threads, which is pin-to-pin compatible with pulpino riscy cores☆20Jul 4, 2025Updated last year
- AI automated Competitor Analysis☆16Aug 6, 2024Updated 2 years ago
- OSVVM Documentation☆37Oct 4, 2026Updated last week
- VHDL functional blocks with their simulations and test sequences☆21Updated this week
- Source repository for BECE Vault — the free, semester-wise notes library for Bachelor in Computer Engineering at Pokhara University. Brow…☆22Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 12 years ago
- AHB3-Lite to Wishbone Bridge☆13Mar 26, 2019Updated 7 years ago
- snap package for nextpnr PnR FPGA toolchain for Xilinx 7 series FPGAs, with Spartan7, Artix7, Zynq7 and Kintex7 support☆30Jul 10, 2024Updated 2 years ago
- SonarQube Cucumber Gherkin Analyzer☆35Jun 28, 2022Updated 4 years ago
- A Firefox/Chrome extension to open IIIF manifest link in your favorite IIIF viewer.☆22Jul 9, 2022Updated 4 years ago
- Open Source Deal Flow Monitoring Infrastructure Built for VCs | Competitive Intelligence Infrastructure Built for Founders☆31Oct 18, 2025Updated 11 months ago
- R2FFT is a fully synthesizable verilog module for doing the FFT on an FPGA or ASIC.☆22Apr 30, 2019Updated 7 years ago
- ☆28Mar 17, 2026Updated 7 months ago
- ☆14Sep 27, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- VHDL package for reading formatted data from comma-separated-values (CSV) files☆23Sep 10, 2013Updated 13 years ago
- TSMC_MPC_PMSM:foc☆15Sep 28, 2018Updated 8 years ago
- Processing Tool Template for Eclipse☆30Apr 14, 2017Updated 9 years ago
- Wishbone to AXI bridge (VHDL)☆51Aug 29, 2019Updated 7 years ago
- ☆27Updated this week
- Digital Interpolation Techniques Applied to Digital Signal Processing☆71Jun 24, 2024Updated 2 years ago
- A multi-threaded microprocessor interleaving as minimum two threads, which is pin-to-pin compatible with pulpino riscy cores☆25Aug 24, 2024Updated 2 years ago