Alternatives and similar repositories for sap-EE2-SS-LAB

Users that are interested in sap-EE2-SS-LAB are comparing it to the libraries listed below

• Aaron-Zhao123 / ELEC50009
  Course material for ELEC50009
  ☆16Updated 10 months ago
• MPA-MLF / Exercises
  Lab files of Machine Learning Fundamentals course taught at the Brno University of Technology
  ☆10Updated 9 months ago
• ultraembedded / riscv
  RISC-V CPU Core (RV32IM)
  ☆1,596Updated 4 years ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆882Updated 3 weeks ago
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆701Updated 2 years ago
• TheThirdOne / rars
  RARS -- RISC-V Assembler and Runtime Simulator
  ☆1,471Updated last year
• stevehoover / LF-Building-a-RISC-V-CPU-Core
  ☆433Updated 9 months ago
• edstott / EEE1labs
  ☆44Updated last month
• riscv-software-src / riscv-tests
  ☆1,092Updated 2 weeks ago
• ultraembedded / biriscv
  32-bit Superscalar RISC-V CPU
  ☆1,147Updated 4 years ago
• y-C-x / HDLBits_Solution
  My solution to the problem set on HDLBits.
  ☆26Updated 5 years ago
• riscv-boom / riscv-boom
  SonicBOOM: The Berkeley Out-of-Order Machine
  ☆2,035Updated 2 weeks ago
• Evensgn / RISC-V-CPU
  RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
  ☆326Updated 7 years ago
• riscv-software-src / riscv-isa-sim
  Spike, a RISC-V ISA Simulator
  ☆2,961Updated last week
• viduraakalanka / HDL-Bits-Solutions
  This is a repository containing solutions to the problem statements given in HDL Bits website.
  ☆367Updated 2 years ago
• 0BAB1 / HOLY_CORE_COURSE
  Learn how to build our own RV32I core, verify it and actually use it. From scratch & with more than 200 pages of detailed tutorial with s…
  ☆305Updated this week
• lowRISC / style-guides
  lowRISC Style Guides
  ☆472Updated last month
• RISCV-MYTH-WORKSHOP / RISC-V-CPU-Core-using-TL-Verilog
  risc-v-myth-workshop-august-Redbeard358 created by GitHub Classroom
  ☆15Updated 5 years ago
• ucb-bar / gemmini
  Berkeley's Spatial Array Generator
  ☆1,149Updated last week
• PrincetonUniversity / openpiton
  The OpenPiton Platform
  ☆746Updated 2 months ago
• riscv / riscv-opcodes
  RISC-V Opcodes
  ☆816Updated last week
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,093Updated last year
• Digilent / digilent-xdc
  A collection of Master XDC files for Digilent FPGA and Zynq boards.
  ☆639Updated last year
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆906Updated 4 years ago
• chipsalliance / riscv-dv
  Random instruction generator for RISC-V processor verification
  ☆1,224Updated 2 months ago
• ucb-bar / chipyard
  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
  ☆2,069Updated 2 weeks ago
• riscv / learn
  Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
  ☆1,264Updated last month
• riscv-non-isa / riscv-asm-manual
  RISC-V Assembly Programmer's Manual
  ☆1,589Updated last week
• Test134n / 32-Verilog-Mini-Projects
  Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …
  ☆22Updated 4 months ago
• abdelazeem201 / ASIC-Design-Roadmap
  The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a c…
  ☆438Updated 5 months ago