yangsu / sublime-vhdlLinks
VHDL Package for Sublime Text
☆59Updated 7 years ago
Alternatives and similar repositories for sublime-vhdl
Users that are interested in sublime-vhdl are comparing it to the libraries listed below
Sorting:
- A 32-bit Microcontroller featuring a RISC-V core☆153Updated 7 years ago
- Regression test suite for Icarus Verilog. (OBSOLETE)☆115Updated 2 years ago
- Core description files for FuseSoC☆124Updated 5 years ago
- VHDL Samples☆69Updated 12 years ago
- The Easy 8-bit Processor☆183Updated 11 years ago
- RISC-V Frontend Server☆63Updated 6 years ago
- CMod-S6 SoC☆42Updated 7 years ago
- ZPUino HDL implementation☆90Updated 6 years ago
- The OpenRISC 1000 architectural simulator☆76Updated 2 months ago
- Collection of open-source peripherals in Verilog☆179Updated 3 years ago
- OpenRISC 1200 implementation☆171Updated 9 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 5 years ago
- ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…☆77Updated 2 years ago
- u-boot-xarm from xilinx git repo with Digilent additions☆32Updated 11 months ago
- public domain tools for FPGAs☆328Updated 8 years ago
- A 32-bit RISC-V processor for mriscv project☆58Updated 8 years ago
- MIPSfpga+ allows loading programs via UART and has a switchable clock☆109Updated 6 years ago
- A very primitive but hopefully self-educational CPU in Verilog☆145Updated 10 years ago
- ☆95Updated 3 years ago
- TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. De…☆148Updated 8 years ago
- LatticeMico32 soft processor☆106Updated 10 years ago
- XUP Basys3 Boards' LIBs and Projects☆27Updated 8 years ago
- RISC-V Linux Port☆36Updated last week
- A utility for Composing FPGA designs from Peripherals☆181Updated 6 months ago
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆18Updated 8 months ago
- A simple RISC-V processor for use in FPGA designs.☆277Updated 11 months ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆65Updated 7 years ago
- A port of FreeRTOS for the RISC-V ISA☆76Updated 6 years ago
- Prepared CentOS6 in Docker to run Xilinx ISE 14.7☆39Updated 2 years ago
- Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools☆126Updated 9 years ago