Alternatives and similar repositories for timing-diagram-stencil

Users that are interested in timing-diagram-stencil are comparing it to the libraries listed below

• intel / multi_power_sequencer
  Multi-Rail Power Sequencer, capable of monitoring and sequencing up to 144 power rails, offers a configurable and rich set of features, s…
  ☆18Updated last month
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆42Updated last week
• mithro / kicad-pmod
  KiCad Library to make it easy to create both host boards and expansion boards and which are compatible with the Digilent "PMOD" specifica…
  ☆39Updated 4 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆69Updated 5 months ago
• bunnie / netlist-checker
  EDIF netlist checker tool
  ☆26Updated 2 years ago
• freecores / freecores.github.io
  Freecores website
  ☆19Updated 8 years ago
• bggardner / can-lite-vhdl
  A lightweight Controller Area Network (CAN) controller in VHDL
  ☆26Updated 7 months ago
• controlpaths / litefury_rp5
  Conecting the Litefury FPGA accelerator to Raspberry Pi 5 over PCIe gen2 x1
  ☆29Updated last year
• jsyk / miilink
  Connecting FPGA and MCU using Ethernet RMII
  ☆23Updated 9 years ago
• freecores / can
  CAN Protocol Controller
  ☆39Updated 10 years ago
• open-tool-forge / summon-fpga-tools
  A simple script to build open-source FPGA tools.
  ☆52Updated 2 years ago
• suoto / fpga_cores
  ☆32Updated 2 years ago
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆179Updated this week
• freecores / pid_controller
  PID controller
  ☆20Updated 10 years ago
• blackmesalabs / s7_mini_fpga
  Example designs for the Spartan7 "S7 Mini" FPGA board
  ☆28Updated 6 years ago
• OpenAutomationTechnologies / VHDL_IP-Cores
  ☆17Updated 4 years ago
• imrickysu / ZYNQ-Custom-Board-Bring-Up-Guide
  This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project th…
  ☆68Updated 7 years ago
• Tommydag / CAN-Bus-Controller
  An CAN bus Controller implemented in Verilog
  ☆46Updated 10 years ago
• BerkeleyLab / Marble-Mini
  "Marble-Mini" Simple FMC carrier board with SFP, 2x FMC, PoE
  ☆19Updated 3 years ago
• gtjennings1 / HyperBUS
  A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  ☆60Updated 6 years ago
• texane / absenc
  Absolute encoder VHDL core
  ☆20Updated 8 years ago
• RISCV-on-Microsemi-FPGA / SoftConsole
  Eclipse based IDE for RISC-V bare metal software development.
  ☆18Updated 5 years ago
• kevinpt / symbolator
  HDL symbol generator
  ☆189Updated 2 years ago
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆52Updated this week
• nematoli / SPI-FPGA-VHDL
  SPI Master and Slave components to be used in all of FPGAs, written in VHDL.
  ☆37Updated 5 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 4 months ago
• ZipCPU / wbscope
  A wishbone controlled scope for FPGA's
  ☆82Updated last year
• mwelling / beagle-wire
  ICE40 FPGA Cape for Beaglebone
  ☆51Updated 4 years ago
• tmbinc / xvcd
  Xilinx Virtual Cable Daemon
  ☆117Updated 3 months ago