Alternatives and similar repositories for xv6

Users that are interested in xv6 are comparing it to the libraries listed below

• dddrrreee / cs140e-23win
  All material for CS140E, winter 2023.
  ☆90Updated last year
• kishanpatel22 / xv6-kernel-threads
  Design and Implementation of kernel level threads for xv6 operating system. Adding system call related to threading environment in xv6 al…
  ☆30Updated 4 years ago
• LearningOS / uCore-Tutorial-Guide-2022S
  ☆18Updated 3 years ago
• cs423-uiuc / cs423-uiuc.github.io
  ☆10Updated this week
• rhysd / riscv32-cpu-chisel
  Learning how to make RISC-V 32bit CPU with Chisel
  ☆69Updated 4 years ago
• lastweek / lastweek.github.io
  Yizhou' Homepage
  ☆52Updated 3 months ago
• Babtsov / jos
  Detailed solutions to assignments of MIT's Operating Systems Engineering course
  ☆56Updated last year
• kvakil / venus
  RISC-V instruction set simulator built for education
  ☆219Updated 3 years ago
• vickiegpt / computer-architecture-revisit-a-quantitative-approach
  This repo stores a more profound view of Computer Architecture: A Quantitative Approach that tells multi-tenancy, virtualize, fine graine…
  ☆26Updated last year
• arch-simulator-sig / chisel-env
  Basic chisel difftest environment for RTL design (WIP
  ☆19Updated 8 months ago
• openeuler-mirror / RISC-V
  ☆25Updated 11 months ago
• alexshuang / write-your-own-ai-compiler
  《自己动手写AI编译器》
  ☆30Updated last year
• howardlau1999 / yatcpu
  Yet another toy CPU.
  ☆93Updated last year
• kazutoiris / MIT6.175
  MIT6.175 & MIT6.375 Study Notes
  ☆44Updated 2 years ago
• skyzh / RISCV-Simulator
  💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visu…
  ☆206Updated 5 years ago
• CMU-SAFARI / Virtuoso
  Virtuoso is a fast, accurate and versatile simulation framework designed for virtual memory research. Virtuoso uses a new simulation met…
  ☆75Updated last month
• jiegec / kb
  My knowledge base
  ☆72Updated 2 weeks ago
• thu-cs-lab / verilog-coding-standard
  Recommended coding standard of Verilog and SystemVerilog.
  ☆36Updated 4 years ago
• XpuOS / xsched
  A scheduling framework for multitasking over diverse XPUs, including GPUs, NPUs, ASICs, and FPGAs
  ☆136Updated last month
• Multi-V-VM / hetGPU
  PTX on XPUs
  ☆81Updated last week
• NVlabs / nvbitfi
  Architecture-level Fault Injection Tool for GPU Application Resilience Evaluation
  ☆76Updated 2 years ago
• jlpteaching / dinocpu
  A teaching-focused RISC-V CPU design used at UC Davis
  ☆151Updated 2 years ago
• pku-minic / first-step
  Take your first step in writing a compiler.
  ☆29Updated 4 years ago
• code-nowww / 2020-USTC-Compiler-Lab-MLIR
  Here is a final lab of Compiler in USTC, focusing on MLIR
  ☆19Updated 4 years ago
• jiangyy / mosaic
  The MOSAIC Operating Systems Model and Checker
  ☆202Updated 2 years ago
• decaf-lang / minidecaf-tests
  The MiniDecaf test cases.
  ☆18Updated 6 months ago
• comparch-security / FlexiCAS
  A Flexible Cache Architectural Simulator
  ☆15Updated 2 months ago
• FDUCSLG / ICS-2021Spring-FDU
  Introduction to Computer Systems (II), Spring 2021
  ☆52Updated 4 years ago
• 61c-teach / sp22-lab-starter
  ☆13Updated 3 years ago
• icsnju / visualinux
  A visualized debugging framework to aid in understanding the Linux kernel.
  ☆168Updated last week