SST Macro Element Library
☆36Nov 5, 2025Updated 3 months ago
Alternatives and similar repositories for sst-macro
Users that are interested in sst-macro are comparing it to the libraries listed below
Sorting:
- SST DUMPI Trace Library☆14Nov 6, 2023Updated 2 years ago
- SST Structural Simulation Toolkit Parallel Discrete Event Core and Services☆193Updated this week
- Tutorial Material from the SST Team☆25Aug 5, 2025Updated 6 months ago
- RISC-V RV32I CPU written in verilog☆10Jul 11, 2020Updated 5 years ago
- A package for constructing sparse tensors from CSV-like data sources.☆11Dec 24, 2017Updated 8 years ago
- GPUDirect Async implementation of HPGMG-FV CUDA☆11May 11, 2018Updated 7 years ago
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 6 years ago
- Yosys plugin for synthesis of Bluespec code☆15Sep 8, 2021Updated 4 years ago
- Visual Analytics Tool for Dragonfly Network-based Supercomputers☆13Dec 8, 2016Updated 9 years ago
- ☆42Jun 3, 2024Updated last year
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Jan 17, 2026Updated last month
- Argument parser for C++☆17Feb 16, 2026Updated 2 weeks ago
- Industry standard I/O for nMigen☆12Apr 23, 2020Updated 5 years ago
- FPU Generator☆20Jul 19, 2021Updated 4 years ago
- Synchronous FIFOs designed in Verilog/System Verilog.☆25Dec 21, 2025Updated 2 months ago
- umbrella project helps you to build up onnc from scratch☆24Mar 14, 2022Updated 3 years ago
- PLCT实验室收集的方舟编译器的相关分析文章和新闻☆22Feb 15, 2021Updated 5 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆25Jul 14, 2020Updated 5 years ago
- HW accelerator mapping optimization framework for in-memory computing☆28Jun 3, 2025Updated 9 months ago
- A polyhedral compiler for hardware accelerators☆59Jul 24, 2024Updated last year
- MPI bindings for Haskell☆46Apr 1, 2023Updated 2 years ago
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆30Jul 17, 2023Updated 2 years ago
- ☆28Nov 20, 2025Updated 3 months ago
- Apio examples☆37Updated this week
- Header-only C++20 wrapper for MPI 4.0.☆47Jan 29, 2026Updated last month
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Sep 30, 2020Updated 5 years ago
- Using VexRiscv without installing Scala☆39Nov 10, 2021Updated 4 years ago
- DAG-based blockchain☆10Apr 20, 2019Updated 6 years ago
- TileFlow is a performance analysis tool based on Timeloop for fusion dataflows☆66Apr 12, 2024Updated last year
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆32Sep 22, 2018Updated 7 years ago
- FPGA-based stochastic gradient descent (powered by ZipML - Low-precision machine learning on reconfigurable hardware)☆33Feb 10, 2020Updated 6 years ago
- ☆13Jan 8, 2020Updated 6 years ago
- Kernel module that makes it possible to create virtual wifi devices each with a virtualized stack.☆11Dec 13, 2011Updated 14 years ago
- ☆11Mar 14, 2023Updated 2 years ago
- Building the linear algebra game!☆10Dec 2, 2024Updated last year
- A Verilog Synthesis Regression Test☆37Jan 19, 2026Updated last month
- This is a hanabi AI bot that can play on http://keldon.net/hanabi/☆11May 29, 2017Updated 8 years ago
- A place to share libraries and utilities that don't belong in the core bsc repo☆38Feb 16, 2026Updated 2 weeks ago
- This version of Chombo is fortran-free and depends on the Proto middleware infrastructure for performance portability.☆10Sep 12, 2025Updated 5 months ago