FPGA Sega in Verilog, for Xilinx Virtex, circa 2002. Has an emulator thrown in, to simplify FPGA debugging.
☆75Nov 17, 2013Updated 12 years ago
Alternatives and similar repositories for sega-system-for-fpga
Users that are interested in sega-system-for-fpga are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- PS/2 Keyboard IP written in VHDL for Xilinx FPGA☆17Jul 11, 2015Updated 10 years ago
- UNIXv7 ported to RISC-V, specifically the Longnan Nano SBC☆13Mar 30, 2023Updated 3 years ago
- A browser-based ZX Spectrum live-coding environment☆13May 21, 2024Updated 2 years ago
- MS-DOS 2.0 restoration project☆10Apr 5, 2024Updated 2 years ago
- A library of VHDL components for Neural Networks☆21Sep 23, 2021Updated 4 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Final Chess Card - Forum64 Edition☆15Mar 31, 2020Updated 6 years ago
- Verilog VPI VGA Simulator using SDL☆11Feb 9, 2015Updated 11 years ago
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 4 years ago
- a barebones bootable platform to run the frotz z-code interpreter inside a VM☆18Oct 17, 2016Updated 9 years ago
- ☆11Jul 28, 2025Updated 11 months ago
- A complete Linux project for the ZYBO. This project helps me during my first steps with embedded Linux. You can find anything necessary t…☆13Oct 8, 2020Updated 5 years ago
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆13Aug 29, 2018Updated 7 years ago
- Node.js bindings for the Capstone disassembler library. https://parasyte.github.io/node-capstone-docs☆60Jul 27, 2017Updated 8 years ago
- A parameterizable Vivado HLS project (C/C++) that implements a master and slave AXI-Stream to AXI-Memory-Mapped data mover (AXI-S default…☆16Aug 29, 2018Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A BSD-style base system using linux kernel☆14Jun 23, 2015Updated 11 years ago
- Rute is a UI library implemented on top of Qt☆38Apr 30, 2021Updated 5 years ago
- Synthesizable FIR filters in VHDL☆14Jul 19, 2019Updated 6 years ago
- A Game Boy emulator written in Go☆21May 9, 2018Updated 8 years ago
- A simple to use VHDL module to display text on VGA display.☆40Dec 16, 2013Updated 12 years ago
- Driving the OLED display on the ZedBoard☆24Jan 30, 2020Updated 6 years ago
- Keeps track of connections to a node http server and provides a way to close connections☆23Feb 20, 2016Updated 10 years ago
- The implementation of AD9371 on KC705☆20Jun 10, 2025Updated last year
- An open-source VHDL library for FPGA design.☆32Jun 2, 2022Updated 4 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- ☆16Aug 9, 2023Updated 2 years ago
- Comparing Different Stochastic Gradien Descent implementations in Haskell against Python☆10Jul 25, 2016Updated 9 years ago
- Move your Amiga 2000 CPU to the Coprocessor slot!☆27Feb 24, 2021Updated 5 years ago
- an object oriented event loop for linux☆29Aug 18, 2011Updated 14 years ago
- FORTH in Zig☆20May 8, 2026Updated last month
- Tip and tricks for hardware board design☆11Jun 23, 2025Updated last year
- VHDL functional blocks with their simulations and test sequences☆20Updated this week
- A city building game for the Anthropocene☆17Apr 25, 2019Updated 7 years ago
- Port of reSID, a MOS6581 SID emulator engine, to Rust☆35Feb 21, 2023Updated 3 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- C implementation of Karplus–Strong synthesis for tiny MCUs☆11Aug 28, 2013Updated 12 years ago
- VHDL Bypass descriptor controller for Xilinx DMA IP for PCIe☆18Oct 23, 2019Updated 6 years ago
- Initial 0.0.1 push☆13Jun 10, 2016Updated 10 years ago
- Python Build System☆16Sep 17, 2021Updated 4 years ago
- OSKM 开源知识地图 Knowledge Map of Open Source☆10Oct 10, 2023Updated 2 years ago
- The web framework nobody asked for, wants, or needs.☆20Dec 14, 2020Updated 5 years ago
- Machine Learning Framework☆10Mar 17, 2016Updated 10 years ago