azonenberg / latentredLinks
Open hardware 48x 1000baseT + 2x 25G SFP28 Ethernet switch
☆23Updated this week
Alternatives and similar repositories for latentred
Users that are interested in latentred are comparing it to the libraries listed below
Sorting:
- Betrusted embedded controller (UP5K)☆45Updated last year
- An FPGA reverse engineering and documentation project☆47Updated this week
- HDL development environment on Nix.☆25Updated 7 months ago
- RFCs for changes to the Amaranth language and standard components☆18Updated 3 weeks ago
- WebAssembly-based Yosys distribution for Amaranth HDL☆27Updated 2 weeks ago
- ☆37Updated last month
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆32Updated 3 years ago
- Unofficial Yosys WebAssembly packages☆71Updated last week
- Bulk scrape and download datasheets from various vendors (insult)☆14Updated 3 years ago
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 2 years ago
- Hot Reconfiguration Technology demo☆40Updated 2 years ago
- System on Chip toolkit for Amaranth HDL☆90Updated 7 months ago
- converts catgirls to gds files☆15Updated 4 years ago
- Notes, scripts and apps to quickfeather board☆10Updated 3 years ago
- User-friendly explanation of Yosys options☆113Updated 3 years ago
- The open-source Zynq 7000 BSP generator for openXC7☆36Updated 4 months ago
- Programmer for the Lattice ECP5 series, making use of FTDI based adaptors☆89Updated 7 months ago
- Small footprint and configurable Inter-Chip communication cores☆58Updated last week
- Playground for experimenting with and sharing short Amaranth programs on the web☆15Updated 3 weeks ago
- ☆13Updated 3 weeks ago
- ☆16Updated 3 years ago
- Experiments with Yosys cxxrtl backend☆49Updated 4 months ago
- A configurable and approachable tool for FPGA debugging and rapid prototyping.☆137Updated last month
- A tool for USB device pass-through using the vfio-user protocol.☆13Updated this week
- Nix flake for openXC7☆38Updated 2 months ago
- ☆22Updated 3 years ago
- Glacial - microcoded RISC-V core designed for low FPGA resource utilization☆84Updated 5 years ago
- PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers☆41Updated last month
- EVEREST: e-Versatile Research Stick for peoples☆36Updated 2 years ago
- Industry standard I/O for Amaranth HDL☆28Updated 7 months ago