Versepelles / Oxygen-Not-Included-ModsLinks
Mods for Oxygen Not Included
☆15Updated 4 years ago
Alternatives and similar repositories for Oxygen-Not-Included-Mods
Users that are interested in Oxygen-Not-Included-Mods are comparing it to the libraries listed below
Sorting:
- Verified visual schematics for all SKY130 Cells☆11Updated 7 months ago
- ☆14Updated 7 months ago
- Bitstream Fault Analysis Tool☆15Updated 2 years ago
- ☆18Updated 3 years ago
- Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verific…☆12Updated 6 years ago
- An automatic place-and-route tool for Minecraft redstone circuits☆25Updated 9 years ago
- An Open-Source Silicon Compiler for Reduced-Complexity Reconfigurable Fabrics☆13Updated this week
- Index of the fully open source process design kits (PDKs) maintained by Google for GlobalFoundries technologies.☆51Updated 3 years ago
- A JSON library implemented in VHDL.☆81Updated 3 weeks ago
- ☆10Updated 4 years ago
- Skill language interpreter☆72Updated 5 years ago
- IRSIM switch-level simulator for digital circuits☆35Updated last month
- Specification of the Wishbone SoC Interconnect Architecture☆49Updated 3 years ago
- Digital Circuit rendering engine☆39Updated 5 months ago
- KLayout technology files for ASAP7 FinFET educational process☆23Updated 2 years ago
- A Sphinx domain providing VHDL language support.☆20Updated 2 years ago
- ☆20Updated 4 years ago
- cocotb extension for nMigen☆17Updated 3 years ago
- Yosys plugin for logic locking and supply-chain security☆23Updated 9 months ago
- Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster☆11Updated 4 years ago
- Fine Grain FPGA Overlay Architecture and Tools☆28Updated 4 years ago
- An Open Source Link Protocol and Controller☆27Updated 4 years ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆50Updated 9 months ago
- FOSSi Foundation Website☆18Updated last year
- A library and command-line tool for querying a Verilog netlist.☆29Updated 3 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆42Updated last year
- Supplemental technology files for ASAP7 PDK with Synopsys design flow☆20Updated 2 years ago
- Reinforcement learning assisted analog layout design flow.☆32Updated last year
- VHDL package to provide C-like string formatting☆15Updated 3 years ago
- Atom linter for Verilog/SystemVerilog, using Icarus Verilog, Slang, Verible or Verilator.☆10Updated 2 years ago