UniversityOfPlymouth-Electronics / Quartus21_UbuntuLinks
Setup instructions for Quartus 21.x and Questa for Ubuntu 20.04
☆14Updated last year
Alternatives and similar repositories for Quartus21_Ubuntu
Users that are interested in Quartus21_Ubuntu are comparing it to the libraries listed below
Sorting:
- A compact USB HID host FPGA core supporting keyboards, mice and gamepads.☆133Updated 4 months ago
- FPGA display controller with support for VGA, DVI, and HDMI.☆230Updated 5 years ago
- SD-Card controller, using either SPI, SDIO, or eMMC interfaces☆306Updated 3 months ago
- Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation☆277Updated last year
- 8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.☆187Updated 5 years ago
- Absolute beginner's guide to the de10-nano☆230Updated 5 months ago
- Waveform Viewer Extension for VScode☆220Updated this week
- YPCB-00338-1P1 Hack☆57Updated 7 months ago
- VCD viewer☆94Updated 2 weeks ago
- ☆135Updated 8 months ago
- A simple, basic, formally verified UART controller☆308Updated last year
- FPGA Logic Analyzer and GUI☆134Updated 2 years ago
- Xilinx Virtual Cable Server for Raspberry Pi☆115Updated 3 years ago
- A simple implementation of a UART modem in Verilog.☆148Updated 3 years ago
- IceChips is a library of all common discrete logic devices in Verilog☆145Updated 8 months ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆80Updated last year
- ☆455Updated 3 weeks ago
- SoC based on VexRiscv and ICE40 UP5K☆159Updated 4 months ago
- Verilog UART☆178Updated 12 years ago
- LiteX boards files☆422Updated last week
- A full-speed device-side USB peripheral core written in Verilog.☆235Updated 2 years ago
- A demo system for Ibex including debug support and some peripherals☆73Updated 2 months ago
- Basic USB-CDC device core (Verilog)☆80Updated 4 years ago
- Simple UART controller for FPGA written in VHDL☆100Updated 4 years ago
- a super-simple pipelined verilog divider. flexible to define stages☆57Updated 6 years ago
- 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.☆26Updated 2 years ago
- TangNano-20K-example☆121Updated last year
- Opensource DDR3 Controller☆377Updated last month
- Verilog SDRAM memory controller☆337Updated 8 years ago
- WISHBONE SD Card Controller IP Core☆125Updated 2 years ago