Alternatives and similar repositories for Gitbook-Computer-Architecture-A-Quantitative-Approach-6th-Chinese:

Users that are interested in Gitbook-Computer-Architecture-A-Quantitative-Approach-6th-Chinese are comparing it to the libraries listed below

• jensen-yan / kisscpu
  国科大一生一芯第二期: RISCV-64 五级流水线CPU
  ☆17Updated 4 years ago
• lmxyy / Computer-Architecture-Task-2
  Riscv32 CPU Project
  ☆89Updated 7 years ago
• runninglinuxkernel / riscv_programming_practice
  ☆204Updated last year
• kazutoiris / MIT6.175
  MIT6.175 & MIT6.375 Study Notes
  ☆37Updated 2 years ago
• chen0031 / Computer-Architecture-A-Quantitative-Approach
  致力于翻译和传播计算机体系结构：量化方法（第6版）
  ☆21Updated 4 years ago
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆130Updated last year
• nicolaswilde / UCAS-Advanced-Computer-Architecture-OpenROAD-flow
  中国科学院大学高级计算机体系结构课程作业：使用OpenROAD-flow完成RTL到GDS全流程
  ☆26Updated 4 years ago
• OSCPU / NutShell-doc
  ☆122Updated 2 years ago
• sunshaoce / rvcc-course
  ☆84Updated last year
• sunshaoce / learning-riscv
  入门RISC-V的手册
  ☆60Updated 8 months ago
• whik / e200_opensource
  The Ultra-Low Power RISC Core
  ☆47Updated 5 years ago
• plctlab / writing-your-first-riscv-simulator
  《从零开始的RISC-V模拟器开发》配套的PPT和教学资料
  ☆217Updated 3 years ago
• meton-robean / ResearchNote
  通过issue和README来记录日常学习研究笔记 关注 机器学习系统，深度学习， LLVM，性能剖视， Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using …
  ☆75Updated 4 years ago
• yuhanzhu612 / OSCPU
  我的一生一芯项目
  ☆16Updated 3 years ago
• USTC-System-Courses / CECS-Lab
  ☆35Updated last year
• sailordiary / computer-systems-ucas
  中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session
  ☆32Updated 7 years ago
• luzhixing12345 / archlab
  NUDT 高级体系结构实验
  ☆35Updated 7 months ago
• CNLHC / Awesome-RISC-V
  ☆29Updated 6 years ago
• cnyangkun / nscscc2018
  nscscc2018
  ☆26Updated 6 years ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆153Updated 6 months ago
• jianzhang96 / AZPRcpu
  AZPR cpu.《CPU自制入门》附录的Verilog代码，其中的日文注释翻译成了中文。
  ☆40Updated 4 years ago
• DawnCarol / DawnCarol
  ☆187Updated 2 weeks ago
• MrAMS / verilogModuleAddPrefix
  verilog module add prefix script 可用于ysyx项目添加学号
  ☆13Updated last year
• ysyx-ta / ysyx-summer-readings
  ☆66Updated 8 months ago
• wataru030-XIAOHEI / My-RISCV64-CORE-writing
  一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .
  ☆27Updated 2 years ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆50Updated 2 years ago
• rv2036 / rv2036-website
  Official website for Jiachen Project (甲辰计划).
  ☆55Updated 4 months ago
• riscv-and-rust-and-decaf / riscv32i-cpu-chisel
  riscv32i-cpu
  ☆19Updated 4 years ago
• weedge / perf-book-cn
  https://github.com/dendibakh/perf-book gitbook在线电子书，翻译成中文原始markdown文档
  ☆84Updated 3 months ago
• kaitoukito / A-Primer-on-Memory-Consistency-and-Cache-Coherence
  A Primer on Memory Consistency and Cache Coherence (Second Edition) 翻译计划
  ☆231Updated 11 months ago