☆18Jun 4, 2026Updated last month
Alternatives and similar repositories for postinstall
Users that are interested in postinstall are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Wokwi-example how the display is initialised for different boards☆12Mar 13, 2023Updated 3 years ago
- Repository containing ULX3S blink LED binaries☆14May 16, 2022Updated 4 years ago
- Edge TPU object detection on Raspberry Pi with Coral USB Accelerator by integrating TensorFlow Lite C++ API and Qt/QML☆11Jun 24, 2019Updated 7 years ago
- A giant Bash script that builds Linux From Scratch☆12Nov 4, 2024Updated last year
- Esp32 code to run deej with just 2 rotary encoders☆14Dec 23, 2024Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆15Apr 13, 2025Updated last year
- List of several designs I have been working through the years to avoid re-designing it again☆16Jun 17, 2024Updated 2 years ago
- FA4-based Relative Attention Kernel developed by TML and Colfax☆17Jul 17, 2026Updated last week
- IOb_SoC version of the Picorv32 RISC-V Verilog IP core☆14Dec 22, 2025Updated 7 months ago
- A tiny FABulous FPGA for TTIHP26a☆15Apr 9, 2026Updated 3 months ago
- ☆39Feb 3, 2025Updated last year
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆13Mar 28, 2025Updated last year
- ☆21Updated this week
- ☆16May 6, 2026Updated 2 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆21May 8, 2025Updated last year
- Agile Hardware Design Course☆15Nov 17, 2025Updated 8 months ago
- Testfield: T593☆15Apr 27, 2026Updated 2 months ago
- The SoC for the introduction to chip design course spring 2026☆19May 22, 2026Updated 2 months ago
- Chisel RTL module of a unified ray tracer datapath pipeline. Supports ray-box intersection, ray-triangle intersection, acceleration for …☆16Jul 18, 2026Updated last week
- 1G‑style Ethernet PHY PCS block in Sky130 using OpenLane☆18Feb 15, 2026Updated 5 months ago
- Repository of files associated with the webinar on analog layout using magic and klayout with Matt Venn.☆17Apr 13, 2023Updated 3 years ago
- This repository contains a RISC-V System-on-Chip (SoC) design files implemented in SystemVerilog☆16Feb 9, 2025Updated last year
- Open source FPGA-based NIC and platform for in-network compute☆16May 22, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- An open-source, JEDEC JESD270-4A-compliant HBM4 memory subsystem (controller + PHY-shim + DFT + RAS + security wrapper) tightly coupled t…☆21Jun 14, 2026Updated last month
- A Chip Design Automation Solution with Open Source EDA Tools.☆15Updated this week
- Personal LFS Repository for my OS☆12Updated this week
- UNICCASS-ICDESIGN-TOOLS is a Docker image that provides a pre-configured environment with essential tools for the design and verification…☆17Mar 19, 2026Updated 4 months ago
- ☆17Dec 25, 2024Updated last year
- ☆19Nov 24, 2025Updated 8 months ago
- IHP Open source SG13G2 Tape Out on April 2025 [Testfield T586]☆17Apr 27, 2026Updated 2 months ago
- A Linux Distro tucanalinux.org☆20Jan 8, 2026Updated 6 months ago
- PyCacheGen: A Highly Configurable Open-Source Generator for Synthesizable Caches☆17Dec 14, 2025Updated 7 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ULX3S Quick Start☆23Oct 8, 2020Updated 5 years ago
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆23Updated this week
- LibreLane full-chip flow template for IHP SG13G2 OpenPDK☆19Apr 20, 2026Updated 3 months ago
- Expose what functional RTL benchmarks leave unanswered. Evidence profiles for AI-generated RTL; research collaborators and design partner…☆18Updated this week
- Open neuromorphic processor architectures. Loihi-class feature set, FPGA-validated.☆18Updated this week
- An SDK for verifiable intent, inline with code: one-line claims above your functions, verified at the rigor you choose and flagged when t…☆33Updated this week
- Processor support packages☆22Feb 2, 2021Updated 5 years ago