Alternatives and similar repositories for MIPS-Architecture-CPU-design

Users that are interested in MIPS-Architecture-CPU-design are comparing it to the libraries listed below

• z4yx / NaiveMIPS-HDL
  Naïve MIPS32 SoC implementation
  ☆115Updated 5 years ago
• trivialmips / TrivialMIPS
  MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
  ☆107Updated 6 years ago
• oscourse-tsinghua / LoongsonCsprj2017-manual
  基于龙芯FPGA开发板的计算机综合系统实验
  ☆25Updated 6 years ago
• nblintao / Computer-Architecture
  A pipelined MIPS CPU supporting 31 MIPS instructions, interrupt and cache.
  ☆20Updated 10 years ago
• xyongcn / LoongsonCsprj2017
  Computer System Project for Loongson FPGA Board in 2017
  ☆52Updated 7 years ago
• Trinkle23897 / mips32-cpu
  奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）
  ☆129Updated 5 years ago
• cnyangkun / nscscc2018
  nscscc2018
  ☆26Updated 6 years ago
• thu-cs-lab / supervisor-rv
  计算机组成原理课程 RISC-V 监控程序，支持 32 位和 64 位
  ☆119Updated 10 months ago
• ustb-owl / Uranus
  Uranus MIPS processor by MaxXing & USTB NSCSCC team
  ☆38Updated 5 years ago
• z4yx / supervisor-mips32
  计算机组成原理课程32位监控程序
  ☆50Updated 5 years ago
• RickyTino / MangoMIPS32
  A softcore microprocessor of MIPS32 architecture.
  ☆40Updated last year
• nxbyte / ARM-LEGv8
  Verilog Implementation of an ARM LEGv8 CPU
  ☆108Updated 6 years ago
• z4yx / ucore-thumips
  uCore MIPS32 porting
  ☆18Updated 5 years ago
• name1e5s / Sirius
  Asymmetric dual issue in-order microprocessor.
  ☆34Updated 5 years ago
• ljlin / MIPS48PipelineCPU
  5 stage pipelined MIPS-32 processor
  ☆57Updated 5 years ago
• hehao98 / RISCV-Simulator
  A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation
  ☆187Updated last year
• hitwh-nscscc / simple-5stage-pipeline-MIPS-imple
  和我一步一步实现一个最简单的、带数据前推及流水线暂停的32位静态五级流水MIPS
  ☆85Updated 4 years ago
• Summer-Summer / ComputerArchitectureLab
  This repository is used to release the experimental assignments of Computer Architecture Course from USTC
  ☆39Updated 6 years ago
• sxtyzhangzk / mips-cpu
  A MIPS CPU implemented in Verilog
  ☆68Updated 7 years ago
• nscscc2019ucas / nscscc2019ucas
  ☆35Updated 5 years ago
• leliyliu / ICS
  智能计算系统课程（陈云霁）课后作业记录
  ☆55Updated 5 years ago
• zach0zhang / Single_instruction_cycle_OpenMIPS
  通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器
  ☆207Updated 3 years ago
• Silverster98 / bit_nscscc_suggestion
  为了更好地帮助后来的同学参加龙芯杯，草拟了这份建议，望对后来人有所帮助
  ☆126Updated 4 years ago
• oscourse-tsinghua / cpu-testcase
  Test cases for MIPS CPU implementation
  ☆12Updated 5 years ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆49Updated last year
• YanB25 / Tomasulo
  An out-of-order execution algorithm for pipeline CPU, implemented by verilog
  ☆40Updated 7 years ago
• thu-cs-lab / thinpad_top
  Project template for Artix-7 based Thinpad board
  ☆48Updated 2 years ago
• MaxXSoft / Fuxi
  Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
  ☆174Updated 4 years ago
• BUAA-SE-Compiling / miniplc0-handbook
  miniplc0 指导书
  ☆22Updated 4 years ago
• KurohaneNioko / Extensive-C0-Compiler
  北航计算机学院 编译原理最高难度课程设计 BUAA SCSE - Extensive C0 Compiler Design
  ☆36Updated 6 years ago