Alternatives and similar repositories for MIPS-Architecture-CPU-design

Users that are interested in MIPS-Architecture-CPU-design are comparing it to the libraries listed below

• OO-guide-2019 / codestyle-guide
  java codestyle guide
  ☆12Updated 6 years ago
• trivialmips / TrivialMIPS
  MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
  ☆106Updated 6 years ago
• KurohaneNioko / Extensive-C0-Compiler
  北航计算机学院 编译原理最高难度课程设计 BUAA SCSE - Extensive C0 Compiler Design
  ☆36Updated 6 years ago
• z4yx / NaiveMIPS-HDL
  Naïve MIPS32 SoC implementation
  ☆115Updated 5 years ago
• xyongcn / LoongsonCsprj2017
  Computer System Project for Loongson FPGA Board in 2017
  ☆52Updated 7 years ago
• RickyTino / MangoMIPS32
  A softcore microprocessor of MIPS32 architecture.
  ☆40Updated last year
• Mistariano / BUAA-CO-Killer
  为北航计算机组成原理设计的CPU测试程序自动生成器
  ☆37Updated 4 years ago
• nblintao / Computer-Architecture
  A pipelined MIPS CPU supporting 31 MIPS instructions, interrupt and cache.
  ☆20Updated 9 years ago
• Trinkle23897 / mips32-cpu
  奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）
  ☆128Updated 5 years ago
• menghuanlater / BUAA_Complier_Design
  北航本科三年级编译课程设计
  ☆40Updated 7 years ago
• menghuanlater / BUAA_MIPS_OS
  北航小操作系统实验代码lab1~lab6
  ☆118Updated 7 years ago
• oscourse-tsinghua / LoongsonCsprj2017-manual
  基于龙芯FPGA开发板的计算机综合系统实验
  ☆25Updated 6 years ago
• zencove-thu / zencove-zoom
  Highly configurable out-of-order MIPS32 processor, capable of booting Linux.
  ☆39Updated last year
• ustb-owl / Uranus
  Uranus MIPS processor by MaxXing & USTB NSCSCC team
  ☆38Updated 5 years ago
• OO-guide-2019 / oo-rules
  oo课程规则文档
  ☆10Updated 6 years ago
• cnyangkun / nscscc2018
  nscscc2018
  ☆26Updated 6 years ago
• JamesDYX / BUAA_OS_Lab
  北航操作系统实验课程
  ☆85Updated 7 years ago
• bit-mips / cpu
  MIPS CPU
  ☆14Updated 4 years ago
• z4yx / ucore-thumips
  uCore MIPS32 porting
  ☆18Updated 5 years ago
• nscscc2019ucas / nscscc2019ucas
  ☆34Updated 5 years ago
• YanB25 / Tomasulo
  An out-of-order execution algorithm for pipeline CPU, implemented by verilog
  ☆40Updated 7 years ago
• sailordiary / computer-systems-ucas
  中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session
  ☆32Updated 8 years ago
• BXYMartin / MIPS-OS
  A Customed Operating System with a Shell for MIPS R3000, Ported from JOS
  ☆23Updated 6 years ago
• OO-guide-2019 / homework-pre
  寒假入门小作业
  ☆12Updated 6 years ago
• xxr5566833 / Compiler
  BUAA Compiler Homework
  ☆13Updated 7 years ago
• OO-guide-2019 / idea-guide-preview
  初步版IDEA使用指南
  ☆23Updated 6 years ago
• ljlin / MIPS48PipelineCPU
  5 stage pipelined MIPS-32 processor
  ☆57Updated 5 years ago
• Mistariano / buaaoo-elevator-test-suit
  为北航面向对象课程电梯单元自动化黑箱测试搭建的IO接口
  ☆15Updated 6 years ago
• huang-jl / LLCL-MIPS
  LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…
  ☆36Updated 3 years ago
• name1e5s / Sirius
  Asymmetric dual issue in-order microprocessor.
  ☆34Updated 5 years ago