Chair-for-Security-Engineering / AGEMALinks
Automated Generation of Masked Hardware
☆19Updated last year
Alternatives and similar repositories for AGEMA
Users that are interested in AGEMA are comparing it to the libraries listed below
Sorting:
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆24Updated last year
- [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4☆37Updated 5 years ago
- Hardware Design of Ascon☆37Updated 3 weeks ago
- SCARV: a side-channel hardened RISC-V platform☆22Updated 4 years ago
- Cryptanalysis of Physically Unclonable Functions☆91Updated last year
- Side-channel analysis setup for OpenTitan☆37Updated 3 months ago
- Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.☆139Updated 3 years ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆61Updated last month
- Post-Quantum Cryptography IP Core (Crystals-Dilithium)☆43Updated this week
- A list of VHDL codes implementing cryptographic algorithms☆27Updated 4 years ago
- Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats☆48Updated 2 years ago
- VexRiscv reference platforms for the pqriscv project☆16Updated last year
- XCrypto: a cryptographic ISE for RISC-V☆92Updated 3 years ago
- Hardware implementation of polynomial multiplication operation of CRYSTALS-KYBER PQC scheme☆40Updated 4 years ago
- PROLEAD - A Probing-Based Leakage Detection Tool for Hardware and Software FIESTA - Fault Injection Evaluation with Statistic…☆41Updated 3 weeks ago
- HW Design Collateral for Caliptra RoT IP☆127Updated this week
- Mutation Cover with Yosys (MCY)☆91Updated last week
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆27Updated 5 years ago
- David Canright's tiny AES S-boxes☆28Updated 11 years ago
- VerMFi: Verification tool for Masked implementations and Fault injection. Set of tools to evaluate resistance of secure hardware against …☆20Updated 6 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆68Updated 3 years ago
- Configurable AES-GCM IP (128, 192, 256 bits)☆38Updated 5 months ago
- This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 is Hex Five's official reference HW p…☆32Updated 2 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆38Updated 4 years ago
- SILVER - Statistical Independence and Leakage Verification☆15Updated 8 months ago
- cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.☆119Updated 5 months ago
- Instruction and files for porting Arm DesignStart to CW305.☆16Updated 2 years ago
- Repo for all activity related to the ODSA Bunch of Wires Specification☆29Updated 2 years ago
- FPGA tool performance profiling☆105Updated last year
- Fine Grain FPGA Overlay Architecture and Tools☆28Updated 4 years ago