toddmaustin / kevlarLinks
KEVLAR memory defenses.
☆17Updated 2 months ago
Alternatives and similar repositories for kevlar
Users that are interested in kevlar are comparing it to the libraries listed below
Sorting:
- Proof-of-concept implementation for the paper "Hammulator: Simulate Now - Exploit Later" (DRAMSec 2023)☆17Updated last year
- Artifact of "Indirector: High-Precision Branch Target Injection Attacks Exploiting the Indirect Branch Predictor" [USENIX Security 2024]☆61Updated 9 months ago
- Microarchitectural exploitation and other hardware attacks.☆92Updated last year
- QARMA block cipher in C☆30Updated 2 years ago
- Proof-of-concept for the GhostWrite CPU bug.☆113Updated 10 months ago
- Student Starter Code for Secure Hardware Design at MIT☆75Updated last year
- The public release of LeftoverLocals code☆66Updated last year
- ☆26Updated 4 months ago
- ☆57Updated 3 months ago
- Pathfinder: High-Resolution Control-Flow Attacks Exploiting the Conditional Branch Predictor☆17Updated 11 months ago
- Proof-of-concept implementation for the paper "Reviving Meltdown 3a" (ESORICS 2023)☆15Updated last year
- Spectre based on Linear Address Masking☆69Updated last year
- Opening Pandora's Box: A Systematic Study of New Ways Microarchitecture can Leak Private Data☆21Updated 2 years ago
- Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores☆16Updated this week
- Medusa Repository: Transynther tool and Medusa Attack☆21Updated 4 years ago
- Proof-of-concept C implementation of AES with masking technique to prevent side-channel analysis attacks☆37Updated 4 years ago
- Collection of RISC-V exploits☆30Updated 5 years ago
- HW interface for memory caches☆28Updated 5 years ago
- ☆16Updated 2 years ago
- Optimized assembly implementations of crypto for the RV32I (RISC-V) architecture☆31Updated 4 years ago
- A migration for the page table entry based side-channel attack agains SGX enclaves.☆16Updated 3 months ago
- TrustZone Trusted Application 0-Days by Design☆20Updated 3 weeks ago
- ☆28Updated 4 months ago
- Using Data Memory-Dependent Prefetchers to Leak Data at Rest☆36Updated 2 years ago
- ☆15Updated 4 years ago
- Proof-of-concept code for the IEEE S&P 2025 paper "Peek-a-Walk: Leaking Secrets via Page Walk Side Channels"☆19Updated 3 months ago
- Artifacts for our ShowTime paper (AsiaCCS '23), including distinguishing cache hits and misses with the human eye.☆12Updated last year
- Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)☆67Updated 2 months ago
- FPGA design and test files for ChipWhisperer-Husky.☆16Updated this week
- Proof-of-concept implementation for the paper "Indirect Meltdown: Building Novel Side-Channel Attacks from Transient Execution Attacks" (…☆22Updated last year