Agent skills for veriloga
☆29Jul 21, 2026Updated last month
Alternatives and similar repositories for veriloga-skills
Users that are interested in veriloga-skills are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Collection for agent skills on analog and mixed-signal (AMS) IC (integrated circuit) design☆31Jun 5, 2026Updated 2 months ago
- 12 agentic skills for analog IC design — architecture, sizing, verification, cross-model review, knowledge graph, and self-evolution. Wor…☆54Jul 2, 2026Updated last month
- A toolbox for ADC modeling, testing, analysis, and calibration, etc.☆135Jul 9, 2026Updated last month
- Agent skill for simulating gmoverid characteristics and gmoverid-based design☆119Jul 7, 2026Updated last month
- Bridge between LLM-Agent and Cadence Virtuoso. A new infrastructure for Agentic Analog and Mixed-Signal Design.☆652Updated this week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- dskill — SKILL Decompiler on RHEL7/CentOS7 (glibc 2.17). Binary-only release.☆17May 12, 2026Updated 3 months ago
- Utilities and a PDK for a custom GaAs process provided as Python packages for use with nazca-degin (https://nazca-design.org/) (fork with…☆16Jul 13, 2026Updated last month
- Python-to-schematic generator for Cadence Virtuoso. Define circuits in Python, auto-generate CDL netlists and schematics.☆27Updated this week
- Port of ciccreator to Python☆21Aug 16, 2026Updated last week
- Extending BookSim2.0 and HotSpot6.0 for Power, Performance and Thermal evaluation of 3D NoC Architectures☆14Aug 9, 2019Updated 7 years ago
- Artifacts for the SCVP lecture☆12Nov 17, 2021Updated 4 years ago
- ☆65Updated this week
- A Verilog Filelist parser in Rust☆11Mar 25, 2022Updated 4 years ago
- Wavious Wlink☆12Oct 28, 2021Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- cadence原理图转visio绘图☆44May 29, 2026Updated 2 months ago
- Claude Code / Codex CLI skill that scaffolds a runnable UVM testbench (APB / AHB-Lite / AXI4-Lite + generic-bus fallback) from an IP sp…☆21Jul 14, 2026Updated last month
- A tool for making password-protected files☆12Jul 6, 2023Updated 3 years ago
- This repository defines a Claude Code skill for working with Verilog☆18Apr 21, 2026Updated 4 months ago
- Designing Full Chip from IEEE Paper using AI in SKY130☆39Jul 4, 2026Updated last month
- Advanced Peripheral Bus (APB) UVM testbench project☆10Apr 9, 2017Updated 9 years ago
- Expose what functional RTL benchmarks leave unanswered. Evidence profiles for AI-generated RTL; research collaborators and design partner…☆20Updated this week
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Feb 9, 2024Updated 2 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Hardware Design, Exploration, and Code Generation for SoC Designers☆12Dec 15, 2019Updated 6 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- ☆12Dec 27, 2022Updated 3 years ago
- ☆23Mar 19, 2026Updated 5 months ago
- ☆61May 22, 2026Updated 3 months ago
- GUI for gds2palace RFIC FEM simulation worklow☆32Updated this week
- Code for "Understanding Metastability in SAR ADCs: Part II: Asynchronous"☆12Apr 19, 2022Updated 4 years ago
- Virtual Breadboard / PCB simulation for Prototyping and Educational Purposes☆15Jun 4, 2023Updated 3 years ago
- 利用C语言和单片机开发了一个自己设计的智能指纹密码锁。包含了PCB图纸; Developed a self-designed smart fingerprint combination lock using C language and microcontroller. P…☆14Sep 3, 2022Updated 3 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- VIP-Bench benchmarks for evaluating secure computation frameworks (e.g., HE, MPC, SE, etc...)☆13Jun 9, 2023Updated 3 years ago
- Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast …☆13Apr 29, 2015Updated 11 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆14Nov 9, 2015Updated 10 years ago
- ☆15Dec 6, 2023Updated 2 years ago
- Hardware Description Language Translator☆17Aug 7, 2026Updated 2 weeks ago
- UVM verification platform for DW_apb_i2c IP core(Master Mode)☆14Aug 21, 2023Updated 3 years ago
- LPC (Linear Predictive Coding) decoder in C++☆13Dec 21, 2016Updated 9 years ago