etri / omnixtendLinks
Unified open-source repository for OmniXtend protocol implementations in C, Verilog, and Chisel, supporting host and memory roles.
☆17Updated 5 months ago
Alternatives and similar repositories for omnixtend
Users that are interested in omnixtend are comparing it to the libraries listed below
Sorting:
- RISC-V IOMMU Specification☆146Updated this week
- Open-source high-performance RISC-V processor☆32Updated 2 months ago
- A matrix extension proposal for AI applications under RISC-V architecture☆162Updated last year
- RISC-V Summit China 2023☆40Updated 2 years ago
- OpenXuantie - OpenC906 Core☆388Updated last year
- An exquisite superscalar RV32GC processor.☆165Updated last year
- RISC-V Packed SIMD Extension☆157Updated this week
- Chisel RISC-V Vector 1.0 Implementation☆131Updated 4 months ago
- RISC-V Architecture Profiles☆172Updated this week
- ☆306Updated 2 weeks ago
- Documentation for XiangShan Design☆42Updated last week
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆32Updated 9 months ago
- A simple superscalar out-of-order RISC-V microprocessor☆237Updated 11 months ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated 2 months ago
- Modern co-simulation framework for RISC-V CPUs☆171Updated this week
- PLIC Specification☆150Updated this week
- ☆71Updated last week
- ☆102Updated 5 months ago
- RISC-V Processor Trace Specification☆205Updated this week
- Open source high performance IEEE-754 floating unit☆89Updated last year
- Unit tests generator for RVV 1.0☆100Updated 3 months ago
- This is a repo for recording and reporting RISCV platform's test and measurement continuously.☆59Updated 2 years ago
- ☆65Updated last month
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆223Updated last month
- RISC-V Development Boards Wandering Project. It is part of the Jiachen Project.☆44Updated last week
- Nix template for the chisel-based industrial designing flows.☆52Updated 9 months ago
- Unofficial guide for ysyx students applying to ShanghaiTech University☆23Updated 11 months ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆194Updated last year
- The Scala parser to parse riscv/riscv-opcodes generate☆22Updated 3 weeks ago
- 香山微架构开放验证第一期:昆明湖BPU模块UT测试模块及环境☆30Updated last year