etri / omnixtendLinks
Unified open-source repository for OmniXtend protocol implementations in C, Verilog, and Chisel, supporting host and memory roles.
☆16Updated 3 months ago
Alternatives and similar repositories for omnixtend
Users that are interested in omnixtend are comparing it to the libraries listed below
Sorting:
- Open source high performance IEEE-754 floating unit☆86Updated last year
- Open-source high-performance RISC-V processor☆31Updated last week
- Unit tests generator for RVV 1.0☆98Updated last month
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆232Updated this week
- A matrix extension proposal for AI applications under RISC-V architecture☆156Updated 10 months ago
- Documentation for XiangShan Design☆37Updated 2 months ago
- ☆301Updated last month
- ☆69Updated 2 years ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆31Updated 8 months ago
- RISC-V IOMMU Specification☆144Updated last week
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated 3 weeks ago
- ☆91Updated 2 months ago
- ☆63Updated 2 months ago
- Instruction Set Generator initially contributed by Futurewei☆302Updated 2 years ago
- OpenXuantie - OpenC906 Core☆380Updated last year
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆50Updated 2 months ago
- Modeling Architectural Platform☆213Updated this week
- CORE-V Family of RISC-V Cores☆310Updated 10 months ago
- The batteries-included testing and formal verification library for Chisel-based RTL designs.☆232Updated last year
- 香山微架构开放验证第一期:昆明湖BPU模块UT测试模块及环境☆29Updated last year
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆221Updated last month
- Modern co-simulation framework for RISC-V CPUs☆165Updated this week
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆307Updated this week
- A Fast, Low-Overhead On-chip Network☆251Updated this week
- Chisel RISC-V Vector 1.0 Implementation☆123Updated 2 months ago
- Vector processor for RISC-V vector ISA☆131Updated 5 years ago
- An energy-efficient RISC-V floating-point compute cluster.☆116Updated this week
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆477Updated 3 weeks ago
- Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor☆46Updated last month
- A Chisel RTL generator for network-on-chip interconnects☆224Updated last month