Alternatives and similar repositories for circuitsense

Users that are interested in circuitsense are comparing it to the libraries listed below

• smarton-empower / Smarton-AI
  ☆15Updated 2 years ago
• QuantaEx / QWallet
  Blockchain Wallet for Coin & ERC20 Tokens
  ☆12Updated 6 years ago
• Anwar-Said / Circuit-Completion-Using-GNNs
  Source code and datasets for Circuit Design Completion using GNNs paper
  ☆10Updated 2 years ago
• OSCC-Project / AiEDA
  RTL-to-Vector-to-GDS
  ☆48Updated 2 weeks ago
• paripath / cdf
  Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format
  ☆13Updated 5 years ago
• devbisme / kinet2pcb
  Utility to convert a KiCad netlist into a PCBNEW .kicad_pcb file.
  ☆14Updated last month
• FOSSEE / Online-NgSpice-Simulator
  Simulate ngSpice netlist on Web
  ☆16Updated 9 years ago
• bunnie / netlist-checker
  EDIF netlist checker tool
  ☆26Updated 3 years ago
• KenKundert / svg_schematic
  Generate SVG schematics and block diagrams without a mouse.
  ☆31Updated 5 months ago
• Xyce / XDM
  This is the XDM netlist converter, used to convert PSPICE and HSPICE netists into Xyce format.
  ☆21Updated last year
• klayoutmatthias / calibre2klayout
  A single-script repo for a script to turn a calibre layer file to a KLayout .lyp file
  ☆13Updated 7 years ago
• aspdac-submission-pcb-layout / PCBBenchmarks
  ☆23Updated 5 years ago
• chenweiphd / HDLGPT
  ☆11Updated last year
• LaurentCabaret / pyVhdl2Sch
  pyVhdl2sch is a python based VHDL to (pdf) schematic converter
  ☆33Updated 6 years ago
• wulffern / aicex
  Files for Advanced Integrated Circuits
  ☆32Updated last week
• gmagno / spyci
  A tiny Python package to parse spice raw data files.
  ☆53Updated 2 years ago
• mbalestrini / gdsiistl
  Converts GDSII files to STL files.
  ☆41Updated 2 years ago
• litaotju / edif-parser
  A c project for EDIF format parse.
  ☆14Updated 9 years ago
• PKU-IDEA / SymDetect
  Layout Symmetry Annotation for Analog Circuits with GraphNeural Networks
  ☆15Updated 2 years ago
• jimwang99 / parser-for-chip-design
  A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).
  ☆32Updated 10 years ago
• unnir / CadenceSKILL-Python
  Inter Process Communication (IPC) between Python and Cadence Virtuoso
  ☆80Updated 8 years ago
• iic-jku / klayout-pex
  Parasitic Extraction for KLayout
  ☆34Updated 2 weeks ago
• dteal / gdsiistl
  Converts GDSII files to STL files.
  ☆51Updated 5 years ago
• f18m / netlist-viewer
  SPICE netlist visualizer
  ☆79Updated last week
• LukeVassallo / RL_PCB
  RL_PCB is a novel learning-based method for optimising the placement of circuit components on a Printed Circuit Board (PCB).
  ☆48Updated last year
• jitendra-bhandari / Masala-CHAI
  ☆87Updated 3 months ago
• dan-fritchman / Netlist
  Parsing and generating popular formats of circuit netlist
  ☆38Updated 3 years ago
• ieee-ceda-datc / datc-rdf-calibrations
  ☆19Updated last year
• d-m-bailey / cvc
  CVC: Circuit Validity Checker. Check for errors in CDL netlist.
  ☆30Updated 5 months ago
• electronics-and-drives / MLCAD22
  Source code for the Paper: "Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards"
  ☆14Updated 3 years ago