daleysoftware / circuitsenseLinks
Convert hand-drawn electrical circuit diagrams to netlists. CircuitSense can be thought of as the equivalent of handwriting recognition for circuits.
☆18Updated 7 years ago
Alternatives and similar repositories for circuitsense
Users that are interested in circuitsense are comparing it to the libraries listed below
Sorting:
- Generate SVG schematics and block diagrams without a mouse.☆31Updated 6 months ago
- Simulate ngSpice netlist on Web☆16Updated 9 years ago
- Cadence Virtuoso Design Management System☆36Updated 3 years ago
- EDIF netlist checker tool☆26Updated 3 years ago
- Converts GDSII files to STL files.☆51Updated 5 years ago
- RTL-to-Vector-to-GDS☆54Updated last month
- pyVhdl2sch is a python based VHDL to (pdf) schematic converter☆33Updated 6 years ago
- This is the XDM netlist converter, used to convert PSPICE and HSPICE netists into Xyce format.☆22Updated last year
- Online viewer of Xschem schematic files☆28Updated 3 weeks ago
- Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format☆13Updated 5 years ago
- Use python for designing circuits (experimental) (deprecated in favor of https://electron-lang.org)☆62Updated 3 years ago
- Files for Advanced Integrated Circuits☆34Updated this week
- A tiny Python package to parse spice raw data files.☆53Updated 3 years ago
- Utility to convert a KiCad netlist into a PCBNEW .kicad_pcb file.☆14Updated 2 months ago
- Donald Amundson's Python interface to OpenAccess IC design data API☆18Updated 15 years ago
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆38Updated 4 years ago
- A single-script repo for a script to turn a calibre layer file to a KLayout .lyp file☆13Updated 7 years ago
- Python Jupyter Notebooks and FPGA designs showcasing what myHDL can do over traditional Verilog or VHDL☆36Updated 7 years ago
- Analog and power building blocks for sky130 pdk☆21Updated 4 years ago
- ☆59Updated 6 months ago
- A current mode buck converter on the SKY130 PDK☆34Updated 4 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆32Updated 2 weeks ago
- BAG framework☆41Updated last year
- A stochastic circuit optimizer for Cadence Virtuoso, using the NSGA-II genetic algorithm.☆12Updated 4 years ago
- RL_PCB is a novel learning-based method for optimising the placement of circuit components on a Printed Circuit Board (PCB).☆49Updated last year
- An example of analogue design using open source IC design tools☆29Updated 4 years ago
- This repository is for (pre-)release versions of the Revolution EDA.☆58Updated 2 weeks ago
- skywater 130nm pdk☆40Updated last week
- GDS visualization, geometry analysis, and parallelized capacitance extraction at field-solver accuracy. MS thesis project.☆24Updated last year
- Source code and datasets for Circuit Design Completion using GNNs paper☆10Updated 2 years ago