daleysoftware / circuitsenseLinks
Convert hand-drawn electrical circuit diagrams to netlists. CircuitSense can be thought of as the equivalent of handwriting recognition for circuits.
☆16Updated 7 years ago
Alternatives and similar repositories for circuitsense
Users that are interested in circuitsense are comparing it to the libraries listed below
Sorting:
- EDIF netlist checker tool☆26Updated 2 years ago
- Converts GDSII files to STL files.☆47Updated 5 years ago
- Cadence Virtuoso Design Management System☆36Updated 2 years ago
- pyVhdl2sch is a python based VHDL to (pdf) schematic converter☆32Updated 5 years ago
- Generate SVG schematics and block diagrams without a mouse.☆28Updated last month
- Simulate ngSpice netlist on Web☆16Updated 8 years ago
- A tiny Python package to parse spice raw data files.☆53Updated 2 years ago
- Converts GDSII files to STL files.☆37Updated last year
- Use python for designing circuits (experimental) (deprecated in favor of https://electron-lang.org)☆61Updated 2 years ago
- Layout Symmetry Annotation for Analog Circuits with GraphNeural Networks☆14Updated 2 years ago
- Translates GDSII into HTML/JS that can be viewed in WebGL-capable web browsers.☆57Updated 4 years ago
- A C++ VLSI circuit schematic and layout database library☆14Updated last year
- ☆18Updated 9 months ago
- Blockchain Wallet for Coin & ERC20 Tokens☆12Updated 6 years ago
- Public repository for Task 6 of OpenROAD project. ML-based PDN synthesis and optimization.☆34Updated 2 years ago
- Utility to convert a KiCad netlist into a PCBNEW .kicad_pcb file.☆15Updated 11 months ago
- GDS visualization, geometry analysis, and parallelized capacitance extraction at field-solver accuracy. MS thesis project.☆22Updated last year
- Source code and datasets for Circuit Design Completion using GNNs paper☆10Updated 2 years ago
- Inter Process Communication (IPC) between Python and Cadence Virtuoso☆78Updated 8 years ago
- Hardware Design Tool - Mixed Signal Simulation with Verilog☆80Updated 7 months ago
- Annealing-based PCB placement tool☆39Updated 5 years ago
- Reinforcement learning assisted analog layout design flow.☆25Updated last year
- Convert an image to a GDS format for inclusion in a zerotoasic project☆13Updated 3 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 4 years ago
- gaw3-20200922 fork with patches to improve remote commands sent from xschem to display waveforms☆15Updated 4 months ago
- Parasitic Extraction for KLayout☆26Updated this week
- Parasitic capacitance analysis of foundry metal stackups☆15Updated 3 months ago
- Loam system models☆16Updated 5 years ago
- BAG framework☆41Updated last year
- Learning to do things with the Skywater 130nm process☆84Updated 4 years ago