Alternatives and similar repositories for sail-riscv

Users that are interested in sail-riscv are comparing it to the libraries listed below

• ThinkOpenly / sail
  Sail architecture definition language
  ☆12Updated 7 months ago
• honggyukim / heaptrace
  a tool that collects and reports heap allocated memory
  ☆14Updated 9 months ago
• fossi-foundation / fossi-foundation-web
  ☆22Updated this week
• XIAOLUHOU / SCA-measurements-and-analysis----Experimental-results-for-textbook
  ☆12Updated 7 months ago
• tenstorrent / tt-kmd
  Tenstorrent Kernel Module
  ☆51Updated last week
• adamwalker / fpga-kvs
  A networked FPGA key-value store written in Clash
  ☆29Updated last year
• Xilinx / nanotube
  ☆105Updated this week
• Johannes4Linux / pciutils
  The PCI Utilities
  ☆23Updated last year
• matbi86 / matbi_fpga_season_1
  to study xilinx fpga using Zybo Z7-20 board
  ☆14Updated last year
• esmil / riscv-linux
  Getting started running RISC-V Linux
  ☆18Updated 4 years ago
• brucehoult / rvv_example
  Simple demonstration of using the RISC-V Vector extension
  ☆47Updated last year
• OFS / linux-dfl
  Linux kernel driver for the Device Feature List framework for FPGA devices
  ☆23Updated 7 months ago
• multifacet / 0sim-workspace
  Tools and experiments for 0sim. Simulate system software behavior on machines with terabytes of main memory from your desktop.
  ☆21Updated 5 years ago
• SimDaSong / 4-bit-cpu
  4 bit CPU (logisim, verilog)
  ☆12Updated 3 years ago
• melver / mc2lib
  Memory consistency model checking and test generation library.
  ☆15Updated 8 years ago
• riscv-non-isa / riscv-c-api-doc
  Documentation of the RISC-V C API
  ☆77Updated this week
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆37Updated 4 years ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆41Updated 6 years ago
• fossi-foundation / fossi-foundation.github.io
  FOSSi Foundation Website
  ☆18Updated 11 months ago
• CTSRD-CHERI / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆32Updated 2 weeks ago
• riscv-non-isa / riscv-semihosting
  ☆32Updated this week
• zhiyisun / enable_arm_pmu
  Enable user-mode access to ARMv7/Linux performance counters
  ☆42Updated 8 years ago
• mit-plv / hemiola
  A Coq framework to support structural design and proof of hardware cache-coherence protocols
  ☆14Updated 3 years ago
• chipsalliance / rocket-chip-blocks
  RTL blocks compatible with the Rocket Chip Generator
  ☆16Updated 5 months ago
• rivosinc / hammer
  Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
  ☆36Updated 3 weeks ago
• Ashwin-Rajesh / Verilog_projects
  Some beginner projects using verilog HDL, along with some documentation on basic syntax
  ☆12Updated 4 years ago
• skudlur / RISCulator
  RISCulator is a RISC-V emulator.
  ☆12Updated 2 years ago
• embench / embench-rt
  Benchmark suite for real-time behavior, including interrupt latency and context switching times
  ☆15Updated 3 years ago
• adwaitjog / mafia
  MAFIA: Multiple Application Framework for GPU architectures
  ☆27Updated 3 years ago
• uec-hanken / tee-hardware
  TEE hardware - based on the chipyard repository - hardware to accelerate TEE
  ☆24Updated 2 years ago