NJU-ProjectN / nexus-am
☆24Updated 4 years ago
Related projects: ⓘ
- ☆163Updated 3 years ago
- 第一届 RISC-V 中国峰会的幻灯片等资料存放☆37Updated last year
- 我的一生一芯项目☆16Updated 2 years ago
- riscv32i-cpu☆18Updated 3 years ago
- nscscc2018☆26Updated 5 years ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆44Updated 9 months ago
- 平头哥玄铁C910的LLVM工具链支持,由PLCT实验室提供,非官方版本☆59Updated 3 years ago
- Gem5 with chinese comment and introduction (master) and some other std gem5 version.☆39Updated 2 years ago
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆40Updated 4 years ago
- 方舟编译入门技术课程的配套代码☆31Updated 4 years ago
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆25Updated 4 years ago
- ☆32Updated 5 years ago
- ☆54Updated this week
- CPU micro benchmarks☆19Updated 2 months ago
- ☆17Updated 2 years ago
- The gem5 Bootcamp 2022 environment. Archived.☆34Updated 2 months ago
- Naïve MIPS32 SoC implementation☆112Updated 4 years ago
- ☆12Updated last week
- Modern co-simulation framework for RISC-V CPUs☆111Updated last week
- Computer System Project for Loongson FPGA Board in 2017☆50Updated 6 years ago
- PLCT实验室的 RISC-V V Spec 实现,基于llvm/llvm-project,rkruppe/rvv-llvm 和 https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi-0.8☆156Updated 2 weeks ago
- Spike, a RISC-V ISA Simulator☆9Updated last year
- ☆51Updated last year
- A softcore microprocessor of MIPS32 architecture.☆39Updated 2 months ago
- 通过issue和README来记录日常学习研究笔记 关注 机器学习系统,深度学习, LLVM,性能剖视, Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using …☆74Updated 4 years ago
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆158Updated 3 years ago
- ☆43Updated this week
- This repo stores a more profound view of Computer Architecture: A Quantitative Approach that tells multi-tenancy, virtualize, fine graine…☆24Updated 7 months ago
- National Student Computer System Capability Challenge☆9Updated 5 years ago
- Yet another toy CPU.☆81Updated 9 months ago