Alternatives and similar repositories for nexus-am

Users that are interested in nexus-am are comparing it to the libraries listed below

• LvNA-system / labeled-RISC-V
  ☆169Updated 3 years ago
• nscscc2019ucas / nscscc2019ucas
  ☆34Updated 5 years ago
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆37Updated 2 years ago
• vickiegpt / computer-architecture-revisit-a-quantitative-approach
  This repo stores a more profound view of Computer Architecture: A Quantitative Approach that tells multi-tenancy, virtualize, fine graine…
  ☆25Updated last year
• lazyparser / becoming-a-compiler-engineer-codes
  方舟编译入门技术课程的配套代码
  ☆29Updated 4 years ago
• cnyangkun / nscscc2018
  nscscc2018
  ☆26Updated 6 years ago
• z4yx / NaiveMIPS-HDL
  Naïve MIPS32 SoC implementation
  ☆115Updated 4 years ago
• RickyTino / MangoMIPS32
  A softcore microprocessor of MIPS32 architecture.
  ☆39Updated 11 months ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆52Updated 5 years ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆48Updated last year
• cnyangkun / nscscc2017
  National Student Computer System Capability Challenge
  ☆9Updated 6 years ago
• ISRC-CAS / c910-llvm
  平头哥玄铁C910的LLVM工具链支持，由PLCT实验室提供，非官方版本
  ☆70Updated 4 years ago
• xyongcn / LoongsonCsprj2017
  Computer System Project for Loongson FPGA Board in 2017
  ☆52Updated 7 years ago
• skyzh / RISCV-Simulator
  💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visu…
  ☆201Updated 4 years ago
• NJU-ProjectN / navy-apps
  ☆14Updated last month
• jlpteaching / dinocpu
  A teaching-focused RISC-V CPU design used at UC Davis
  ☆147Updated 2 years ago
• Lingrui98 / RISC-V-book
  A translation project of the RISC-V reader
  ☆175Updated last year
• howardlau1999 / yatcpu
  Yet another toy CPU.
  ☆91Updated last year
• ljwljwljwljw / DiplomaticBackend
  ☆17Updated 3 years ago
• trivialmips / TrivialMIPS
  MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
  ☆106Updated 6 years ago
• plctlab / llvm-project
  PLCT实验室的 RISC-V V Spec 实现，基于llvm/llvm-project，rkruppe/rvv-llvm 和 https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi-0.8
  ☆160Updated 5 months ago
• plctlab / plct-toolbox
  PLCT工具箱
  ☆31Updated 3 years ago
• yuhanzhu612 / OSCPU
  我的一生一芯项目
  ☆16Updated 3 years ago
• JamesAslan / MicroArchBench
  ☆72Updated 7 months ago
• riscv-and-rust-and-decaf / riscv32i-cpu-chisel
  riscv32i-cpu
  ☆18Updated 4 years ago
• ustb-owl / Uranus
  Uranus MIPS processor by MaxXing & USTB NSCSCC team
  ☆38Updated 5 years ago
• MaxXSoft / Fuxi
  Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
  ☆172Updated 3 years ago
• ljlin / MIPS48PipelineCPU
  5 stage pipelined MIPS-32 processor
  ☆56Updated 5 years ago
• cry-daniel / Computer-Architecture-Learning
  ☆61Updated 2 years ago
• plctlab / plct-spike
  Spike, a RISC-V ISA Simulator
  ☆9Updated last year