Neural Network framework using Backpropogation in C
☆79Jan 23, 2022Updated 4 years ago
Alternatives and similar repositories for Neural-Network-framework-using-Backpropogation-in-C
Users that are interested in Neural-Network-framework-using-Backpropogation-in-C are comparing it to the libraries listed below
Sorting:
- Available when training a Neural Network, or an Autoencoder.☆24Dec 14, 2013Updated 12 years ago
- T2EX (T-Kernel 2.0 Extension)☆11Jan 21, 2025Updated last year
- ☆48Sep 22, 2018Updated 7 years ago
- ☆19Dec 19, 2018Updated 7 years ago
- matrix-coprocessor for RISC-V☆31Feb 27, 2026Updated 3 weeks ago
- Lemberg is a time-predictable VLIW processor optimized for performance.☆21May 8, 2013Updated 12 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆32Feb 7, 2025Updated last year
- ☆24Oct 24, 2022Updated 3 years ago
- CORE-V eXtension Interface compliant RISC-V [F|Zfinx] Coprocessor☆14Nov 12, 2025Updated 4 months ago
- Final project for Computer Architecture FA16☆20Jan 5, 2017Updated 9 years ago
- A RISC-V assembler library for Scala/Chisel HDL projects☆16Mar 5, 2026Updated 2 weeks ago
- nanovg sokol renderer and example☆22Oct 25, 2025Updated 4 months ago
- SystemC to Verilog Synthesizable Subset Translator☆12May 12, 2023Updated 2 years ago
- Automated Analysis Framework for Simulink/Stateflow☆15Jul 25, 2023Updated 2 years ago
- An almost empty chisel project as a starting point for hardware design☆35Jan 27, 2025Updated last year
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆24Nov 7, 2018Updated 7 years ago
- ☆20Mar 3, 2026Updated 2 weeks ago
- 📓 A LaTeX template for writing thesis report for RUET☆12Jan 7, 2016Updated 10 years ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆19Oct 22, 2025Updated 5 months ago
- ☆25Aug 9, 2022Updated 3 years ago
- A Simple Hierarchical State Machine☆26May 5, 2015Updated 10 years ago
- This is the final project for the BP NN FPGA implementation☆11Jan 14, 2017Updated 9 years ago
- The project is open source and open hardware, the purpose of which is to create a PLC based on STM32 MCU's.☆63Jan 5, 2018Updated 8 years ago
- Event system / event bus, message channel for embedded systems☆15Mar 15, 2018Updated 8 years ago
- Experiments with fixed function renderers and Chisel HDL☆60Mar 31, 2019Updated 6 years ago
- Convolutional Neural Network (CNN) image classification of handwritten digits in Xilinx FPGA☆14Sep 12, 2019Updated 6 years ago
- Compression of images with JPEG algorithm using python and Huffman codes.☆10Apr 12, 2020Updated 5 years ago
- A collection of benchmarks and tests for the Patmos processor and compiler☆18Dec 2, 2024Updated last year
- Submission template for Tiny Tapeout 7 - Verilog HDL Projects☆22May 30, 2024Updated last year
- SRAM build space for SKY130 provided by SkyWater.☆25Oct 20, 2021Updated 4 years ago
- Kevin's RTOS for AVR microcontrollers☆27Nov 17, 2017Updated 8 years ago
- Lipsi: Probably the Smallest Processor in the World☆88Apr 15, 2024Updated last year
- An Open Source Link Protocol and Controller☆28Aug 1, 2021Updated 4 years ago
- ☆27Aug 2, 2021Updated 4 years ago
- STM32 Hiperface Encoder circuit and software☆11Nov 14, 2023Updated 2 years ago
- Ocaml code from Writing an Interpreter in Go☆11Aug 16, 2019Updated 6 years ago
- vscode support for chez shame☆10Dec 3, 2019Updated 6 years ago
- Paper Collection of Deep Learning Hardware Accelerator☆17Jun 2, 2019Updated 6 years ago
- VS Code extension that recommends using the Windows Subsystem for Linux (WSL) and the Remote WSL extension.☆12Mar 3, 2026Updated 2 weeks ago