kkudrolli / Team-SDK-545Links
An FPGA design project by Kais Kudrolli, Sohil Shah, and DongJoon Park for 18-545 at Carnegie Mellon University.
☆10Updated 8 years ago
Alternatives and similar repositories for Team-SDK-545
Users that are interested in Team-SDK-545 are comparing it to the libraries listed below
Sorting:
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆66Updated 3 years ago
- A place to keep my synthesizable verilog examples.☆49Updated 8 months ago
- FGPU is a soft GPU architecture general purpose computing☆60Updated 5 years ago
- 32 Bit RippleCarry, CarrySkip, CarrySelect, CarryIncrement, Sklansky, Brent-Kung, Kogge-Stone and CarryLookahead adders with their intern…☆27Updated 7 years ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆105Updated 7 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆219Updated 5 years ago
- ☆110Updated 7 years ago
- Website for the OpenROAD tutorial held at the MICRO 2022 conference☆32Updated 3 years ago
- CNN accelerator☆27Updated 8 years ago
- ☆40Updated last year
- FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.☆62Updated last year
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆94Updated 11 months ago
- ☆82Updated last year
- Riscy Processors - Open-Sourced RISC-V Processors☆73Updated 6 years ago
- Universal number Posit HDL Arithmetic Architecture generator☆68Updated 6 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆67Updated 9 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- ☆14Updated 2 years ago
- Architecting and Building High Speed SoCs, published by Packt☆29Updated 2 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- Hand-written HDL code and C-based HLS designs for K-means clustering implementations on FPGAs☆48Updated 8 years ago
- Lipsi: Probably the Smallest Processor in the World☆88Updated last year
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- Open-Source HLS Examples for Microchip FPGAs☆49Updated 3 weeks ago
- Yet Another RISC-V Implementation☆99Updated last year
- For contributions of Chisel IP to the chisel community.☆69Updated last year
- Hot & Spicy tool suite☆23Updated 3 years ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆31Updated 4 years ago