Alternatives and similar repositories for mars:

Users that are interested in mars are comparing it to the libraries listed below

• noteed / riscv-hello-c
  Bare metal RISC-V hello world in C
  ☆18Updated 5 years ago
• kvakil / venus
  RISC-V instruction set simulator built for education
  ☆191Updated 2 years ago
• racerxdl / riscv-online-asm
  RISC-V Online Assembler using Emscripten, Gnu Binutils
  ☆46Updated last year
• nullpo-head / xv6-mips
  A MIPS port of xv6
  ☆71Updated 8 years ago
• amirbawab / EasyCC-CPP
  Easy Compiler Compiler written in C++
  ☆23Updated 7 years ago
• ksco / chibicc-riscv
  A fork of chibicc ported to RISC-V assembly.
  ☆38Updated 2 years ago
• ThaumicMekanism / venus
  RISC-V instruction set simulator built for education
  ☆154Updated 2 years ago
• revyos / revyos
  Yet another Linux Distro for RISC-V!
  ☆57Updated this week
• grantae / OpenMIPS
  A full implementation of the MIPS32 Release 1 ISA, including virtual memory, TLB, instruction and data caches, interrupts and exceptions,…
  ☆68Updated 5 years ago
• a-darwish / cuteOS-references
  Documentation, references, and collected academic research for the cuteOS Kernel.
  ☆37Updated 9 years ago
• nomtats / gdbserver-stub
  ☆16Updated 11 months ago
• skyzh / mips-cpu
  💻 A 5-stage pipeline MIPS CPU implementation in Verilog.
  ☆28Updated 4 years ago
• RISCVtestbed / rvv-rollback
  Translate RISC-V Vector Assembly from v1.0 to v0.7
  ☆28Updated 4 months ago
• skyzh / RISCV-Simulator
  💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visu…
  ☆199Updated 4 years ago
• gensim-project / gensim
  The GenSim project
  ☆14Updated last year
• vortexgpgpu / pocl
  a clone of POCL that includes RISC-V newlib devices support and Vortex
  ☆37Updated 7 months ago
• aliireza / CacheDirector
  CacheDirector - Sending Packets to the Right Slice by Exploiting Intel Last-Level Cache Addressing
  ☆12Updated 5 years ago
• fmash16 / riscv_emulator
  A basic working RISCV emulator written in C
  ☆62Updated 11 months ago
• michaelengel / xv6-d1
  Port of MIT's xv6 OS to the Nezha RISC-V board with Allwinner D1 SoC
  ☆103Updated 2 years ago
• drh / drhanson
  Software and documentation, mostly from the 80s and 90s
  ☆23Updated 9 years ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆30Updated 9 months ago
• dramforever / opensbi-h
  WIP: A fork of OpenSBI, with software-emulated hypervisor extension support
  ☆35Updated last year
• freecores / mcs-4
  4004 CPU and MCS-4 family chips
  ☆37Updated 10 years ago
• Jonathan2251 / lbt
  Develop toolchain based on llvm to for Cpu0 processor
  ☆45Updated last year
• embecosm / gnu-superopt
  The GNU Superoptimizer
  ☆26Updated 10 years ago
• char-fish-after-lunch / SystemOnCat
  An SoC with multiple RISC-V IMA processors.
  ☆19Updated 6 years ago
• msyksphinz-self / riscv-isadoc
  ☆30Updated 9 months ago
• TheRiscGuy / Veecom
  Simple Yet Powerful RISC-V Computer
  ☆115Updated this week
• Kenny2github / V2MC
  Synthesize Verilog to Minecraft redstone
  ☆11Updated 2 months ago
• skyzh / mips-simulator
  💻 A 5-stage pipeline MIPS CPU design in Haskell.
  ☆36Updated 4 years ago