Alternatives and similar repositories for jasmine:

Users that are interested in jasmine are comparing it to the libraries listed below

• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• intel / cNVMe
  An NVMe Device Simulation Library.
  ☆50Updated 2 years ago
• lowRISC / lowrisc-fpga
  Untethered (stand-alone) FPGA implementation of the lowRISC SoC
  ☆54Updated 5 years ago
• DFC-OpenSource / ox-ctrl
  OX: Computational Storage SSD Controller
  ☆51Updated 5 months ago
• Cosmos-OpenSSD / Cosmos-OpenSSD
  ☆42Updated 7 years ago
• RSPwFPGAs / virtio-fpga
  A platform for emulating Virtio devices with FPGAs
  ☆25Updated 3 years ago
• openhwgroup / core-v-sw
  Main Repo for the OpenHW Group Software Task Group
  ☆15Updated this week
• riscv / configuration-structure
  RISC-V Configuration Structure
  ☆37Updated 2 months ago
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆78Updated 4 years ago
• NetTLP / adapter
  An FPGA-based NetTLP adapter
  ☆24Updated 4 years ago
• westerndigitalcorporation / omnixtend
  An open standard Cache Coherent Fabric Interface repository
  ☆65Updated 5 years ago
• riscv / riscv-smbios
  RISC-V SMBIOS Type 44 Spec
  ☆12Updated last year
• sifive / freedom-devicetree-tools
  A linker script generator for SiFive's Freedom platform
  ☆31Updated 3 years ago
• riscv-non-isa / riscv-uefi
  ☆28Updated 2 years ago
• Cosmos-OpenSSD / Cosmos-plus-OpenSSD
  Cosmos OpenSSD + Hardware and Software source distribution
  ☆202Updated 2 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆69Updated 5 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 3 years ago
• openrisc / or1ksim
  The OpenRISC 1000 architectural simulator
  ☆72Updated 4 months ago
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆18Updated 5 years ago
• pulp-platform / trace_debugger
  Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.
  ☆18Updated 10 months ago
• pcie-bench / pciebench-netfpga
  pcie-bench code for NetFPGA/VCU709 cards
  ☆34Updated 6 years ago
• Distrotech / memtest86
  http://www.memtest.org
  ☆54Updated 9 years ago
• aliireza / CacheDirector
  CacheDirector - Sending Packets to the Right Slice by Exploiting Intel Last-Level Cache Addressing
  ☆12Updated 5 years ago
• rwmjones / fedora-riscv-kernel
  Linux kernel build scripts and patches for Fedora/RISC-V
  ☆16Updated 6 years ago
• texane / vpcie
  implement PCIE devices using C or VHDL and test them against a QEMU virtualized architecture
  ☆102Updated 6 years ago