Alternatives and similar repositories for Violet

Users that are interested in Violet are comparing it to the libraries listed below

• Alignof / hikami
  A lightweight Type-1 hypervisor for RISC-V H-extension, featuring RISC-V extension emulation.
  ☆51Updated 3 weeks ago
• NextMicon / NextMiconIDE
  🛠️ Graphical IDE for NextMicon
  ☆28Updated last year
• caprese-project / caprese
  Caprese is a microkernel that protects resources with capability-based security.
  ☆18Updated last year
• ciniml / seccamp_2022_riscv_cpu
  セキュリティキャンプ 2022 Y4 RISC-V CPU自作ゼミ 講義資料
  ☆29Updated last year
• i4kimura / chisel-minicpu
  ☆14Updated 5 years ago
• shioyadan / advanced-computer-organization
  ☆162Updated 11 months ago
• horizon2038 / A9N
  A9N is a Capability-Based Microkernel in C++ with a Hardware Abstraction Layer (HAL) for easy portability and enhanced security.
  ☆46Updated last week
• vaj / riscv-os
  A tiny educational OS for RISC-V
  ☆25Updated 10 months ago
• i4kimura / chip_architect
  Translation of http://chip-architect.com/news/2003_09_21_Detailed_Architecture_of_AMDs_64bit_Core.html
  ☆11Updated 6 years ago
• shibatchii / RISC-V
  RISC-V documentation transrate to Japanese.
  ☆73Updated 3 years ago
• moizumi99 / m99_riscv_emulator
  Simple RISC-V emulator
  ☆16Updated 4 years ago
• sozysozbot / 2kmcc
  ☆29Updated 2 years ago
• horizon2038 / Nun
  Runtime for creating OS to use A9N Microkernel
  ☆11Updated last month
• HidenoriMatsubayashi / evisor
  Light-weight Bare Metal Hypervisor (Type 1) written in C++
  ☆61Updated 11 months ago
• lemolatoon / toy-shakyo
  ☆14Updated last year
• ciniml / seccamp_riscv_cpu
  セキュリティ・キャンプ 2022-2024 RISC-V CPU自作ゼミ 資料置き場
  ☆37Updated 4 months ago
• opensource-jp / Open-Source-AI
  Japanese translation of Open Source AI Definition
  ☆25Updated 9 months ago
• k-mrm / Pilevisor
  aarch64 thin hypervisor for resource aggregation
  ☆36Updated 4 months ago
• RIKEN-RCCS / MilvusVisor
  A thin-hypervisor that runs on aarch64 CPUs.
  ☆96Updated 2 months ago
• msyksphinz-self / swimmer_riscv
  Instruction set simulator for RISC-V
  ☆53Updated 5 years ago
• takenobu-hs / cpu-assembly-examples
  CPU assembly examples
  ☆83Updated last year
• msyksphinz-self / support_ca_llvm_book
  ☆142Updated last year
• nananapo / veryl-riscv-book
  Let's write RISC-V CPU in Veryl!
  ☆50Updated 2 months ago
• tier4 / awkernel
  Awkernel: realtime operating system written in Rust
  ☆189Updated this week
• aitrios / aitrios-edge-device-core
  Official module for connecting edge devices to AITRIOS console.
  ☆18Updated this week
• cpu-dev / cpu-dev.github.io
  ☆16Updated 5 years ago
• pandax381 / mikanos-net
  Educational Operating System
  ☆22Updated 4 years ago
• dtc-work / Qumico
  ☆37Updated 2 years ago
• VLSI-JP / VLSI-JP.github.io
  ☆26Updated last week
• otamajakusi / riscv-step-by-step
  RISC-V kernel step-by-step implmenetation
  ☆12Updated 5 years ago