m-labs / ionpak
A modern, low-cost universal controller for hot-cathode ionization vacuum gauges. (WIP)
☆19Updated 5 years ago
Alternatives and similar repositories for ionpak:
Users that are interested in ionpak are comparing it to the libraries listed below
- A Qt5 based free VLSI development tool☆30Updated 6 years ago
- FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)☆53Updated 3 years ago
- A Verilog parser for Haskell.☆34Updated 3 years ago
- Syntax highlighting for various PCB (Printed Circuit Board) formats.☆20Updated 2 years ago
- a simple C-to-Verilog compiler☆48Updated 7 years ago
- A 6800 CPU written in nMigen☆48Updated 3 years ago
- Reed Solomon BCH encoder and decoder☆23Updated 6 years ago
- Finding the bacteria in rotting FPGA designs.☆13Updated 4 years ago
- ☆58Updated last year
- A collection of HDL cores written in MyHDL.☆12Updated 9 years ago
- 64-bit MISC Architecture CPU☆12Updated 8 years ago
- Slides for the talk I have very soon☆12Updated 6 years ago
- ICE40 FPGA Cape for Beaglebone☆50Updated 4 years ago
- A bit-serial CPU☆18Updated 5 years ago
- A central place to organize and publish all of my hobbyist electronics knowledge and projects.☆29Updated 7 years ago
- iCE40 floorplan viewer☆24Updated 6 years ago
- experimentation with STEP/IGES visualization in kicad via OCE☆13Updated 3 years ago
- The CAT Board is a Raspberry Pi HAT with a Lattice iCE40HX FPGA.☆61Updated 11 months ago
- ☆23Updated 9 years ago
- Everything to do with the XuLA FPGA board: schematics, layout, firmware, example FPGA designs, documentation, etc.☆37Updated 10 years ago
- ☆11Updated 7 years ago
- Qucsator-RF is RF circuit simulation kernel for Qucs-S☆17Updated last month
- 1st Testwafer for LibreSilicon☆28Updated 5 years ago
- This repository contains software for BeagleWire. It is a realization of my project for GSOC-2017☆46Updated 6 years ago
- Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)☆32Updated 3 years ago
- A template project for the ULX3S ECP5 FPGA board using only Open Source Software☆13Updated 6 years ago
- Altera MAX V bitstream documentation -- CLEANUP PENDING☆19Updated 4 years ago
- Project Trellis database☆13Updated last year
- autorouter forked from https://www-soc.lip6.fr/git/coriolis.git☆15Updated 6 years ago
- A mixed signal netlist language (pre-alpha)☆60Updated 6 years ago