ylyamin / RT-Thread-on-Allwinner-D1HLinks
Experimentation with the RT-Thread Operating System with the Allwinner D1H
☆11Updated 11 months ago
Alternatives and similar repositories for RT-Thread-on-Allwinner-D1H
Users that are interested in RT-Thread-on-Allwinner-D1H are comparing it to the libraries listed below
Sorting:
- ☆20Updated 3 months ago
- Minimal assembler and ecosystem for bare-metal RISC-V development☆55Updated last year
- A very simple RISC-V ISA emulator.☆38Updated 4 years ago
- A baremetal experiment of Allwinner D1, without FEL☆33Updated 2 years ago
- One Page CPU Project - CPU, Assembler & Emulator each in a single page of code☆82Updated last year
- Small 32-bit RISC-V CPU with a half-width datapath inspired by the 68000☆16Updated last year
- Port of MIT's xv6 OS to 32 bit RISC V☆41Updated 3 years ago
- Tiny RISC-V machine code monitor written in RISC-V assembly.☆54Updated 3 months ago
- ☆34Updated 5 years ago
- ☆11Updated 5 years ago
- BillBe is an (incomplete) Hobbit BeBox emulator.☆13Updated 8 years ago
- Allwinner A20 bare metal samples☆10Updated 8 years ago
- Patched sources/configs for RISC-V Linux with musl-based toolchain targeting 8 MB RAM☆24Updated 3 years ago
- Standalone C compiler for RISC-V and ARM☆93Updated last year
- Port TCC (Tiny C Compiler) to support Risc-V 32 targets (specifically for the ESP32-C3). This project is a work-in-progress and is not cu…☆72Updated last month
- A ZipCPU demonstration port for the icoboard☆19Updated 4 years ago
- GNU toolchain for RISC-V, including GCC. Tweaked for microcontrollers.☆33Updated this week
- Xv6 ports for RISC-V☆13Updated 11 months ago
- ☆53Updated 8 years ago
- Memory system and UART implemented on Tang Nano 20K for DEC DCJ11 PDP-11 Processor☆76Updated last month
- buildroot fork☆38Updated 4 months ago
- Small footprint, low dependency, C code implementation of a FAT16 & FAT32 driver.☆73Updated 6 years ago
- Work to enable a Classic Mac (24-bit 68000) with ~16MB of RAM.☆11Updated 2 years ago
- ☆12Updated 5 years ago
- 🔌 CPU86 - Free VHDL CPU8088 IP core - ported to Papilio and Max1000 FPGA☆45Updated 2 months ago
- Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).☆56Updated 2 years ago
- J-Core J2/J32 5 stage pipeline CPU core☆54Updated 4 years ago
- 16 bit RISC-V proof of concept☆24Updated 3 weeks ago
- Version 2 of my Crazy Small CPU☆71Updated 6 years ago
- Port of MIT's xv6 OS to the Nezha RISC-V board with Allwinner D1 SoC☆107Updated 2 years ago