Alternatives and similar repositories for multizone-api

Users that are interested in multizone-api are comparing it to the libraries listed below

• hex-five / multizone-sdk
  MultiZone® Security TEE is the quick and safe way to add security and separation to any RISC-V processors. The RISC-V standard ISA doesn'…
  ☆85Updated last year
• keystone-enclave / riscv-pk
  Security monitor for Keystone Enclave (mirror of riscv-pk). Will be deprecated when openSBI port is ready
  ☆35Updated 4 years ago
• hex-five / multizone-sdk-arm
  MultiZone® Security TEE for Arm® Cortex®-M is the quick and safe way to add security and separation to any Cortex-M based device. MultiZo…
  ☆14Updated last year
• ARM-software / TZ-TRNG
  TrustZone True Number Generator
  ☆37Updated 3 years ago
• hex-five / multizone-linux
  MultiZone® Security Enclave for Linux
  ☆18Updated 3 years ago
• scarv / xcrypto
  XCrypto: a cryptographic ISE for RISC-V
  ☆93Updated 2 years ago
• hex-five / multizone-iot-sdk
  MultiZone® Trusted Firmware is the quick and safe way to build secure IoT applications with any RISC-V processor. It provides secure acce…
  ☆20Updated last year
• open-isa-org / open-isa.org
  Software, tools, documentation for Vegaboard platform
  ☆64Updated 5 years ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆36Updated 4 years ago
• keystone-enclave / keystone-demo
  Demo host and enclave applications exercising most functionality.
  ☆31Updated last year
• RISCV-on-Microsemi-FPGA / FreeRTOS
  FreeRTOS for RISC-V
  ☆26Updated 6 years ago
• lowRISC / rocket
  ☆31Updated 7 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆57Updated 5 years ago
• polarfire-soc / meta-polarfire-soc-yocto-bsp
  PolarFire SoC yocto Board Support Package
  ☆55Updated 2 months ago
• hex-five / multizone-fpga
  This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 is Hex Five's official reference HW p…
  ☆30Updated last year
• emb-riscv / specs-markdown
  The preliminary 'RISC-V microcontroller profile' specs; for convenience, use markdown.
  ☆28Updated 3 years ago
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆59Updated last month
• ThalesGroup / RISC-V-IoT-Contest
  RISC-V Soft CPU Security Contest by Thales and Microchip Technology
  ☆11Updated 5 years ago
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆20Updated 5 years ago
• CHERIoT-Platform / cheriot-sail
  Sail code model of the CHERIoT ISA
  ☆38Updated 2 weeks ago
• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆50Updated 8 years ago
• intel / pfr-wilson-city
  ☆24Updated 8 months ago
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆87Updated 5 years ago
• mjosaarinen / lwaes_isa
  [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4
  ☆36Updated 4 years ago
• rsnikhil / RISCV_ISA_Formal_Spec_in_BSV
  A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)
  ☆20Updated 7 years ago
• microsoft / cheriot-ibex
  cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
  ☆106Updated this week
• fractalclone / zephyr-riscv
  Zephyr port to riscv architecture
  ☆24Updated 7 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• sbates130272 / docker-riscv
  A Dockerfile for the tools needed to develop for the RISC-V open-source CPU
  ☆25Updated 6 years ago
• SRI-CSL / l3riscv
  An executable specification of the RISCV ISA in L3.
  ☆42Updated 6 years ago