Implementation of the core Transformer architecture in pure C
☆14Sep 8, 2024Updated 2 years ago
Alternatives and similar repositories for C-Transformer
Users that are interested in C-Transformer are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Load and run Llama from safetensors files in C☆16Oct 24, 2024Updated last year
- High Performance Network Laboratory WebPage☆27Sep 22, 2026Updated 3 weeks ago
- Track line editing history in VSCode☆13Feb 7, 2026Updated 8 months ago
- ☆11Nov 22, 2025Updated 11 months ago
- Accelerate multihead attention transformer model using HLS for FPGA☆13Dec 7, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Inflate 2D svg files to 3D STL or OpenSCAD files☆14Nov 16, 2020Updated 5 years ago
- ☆13Apr 9, 2018Updated 8 years ago
- Categorial Variation Database☆11Nov 27, 2021Updated 4 years ago
- Based on Simulating an Epidemic by 3Blue1Brown, this interactive simulation lets the user explore their ideas experimentally and quantita…☆12Nov 1, 2020Updated 5 years ago
- FPGA Implementation of Image Processing for MNIST Dataset Based on Convolutional Neural Network Algorithm (CNN)☆11Dec 12, 2023Updated 2 years ago
- debug segfault☆18Jan 19, 2016Updated 10 years ago
- Implementation of the BitLinear layer from: The Era of 1-bit LLMs: All Large Language Models are in 1.58 Bits☆13Sep 11, 2024Updated 2 years ago
- Ultra-lightweight C++ inference engine for BitMamba-2 (1.58-bit SSM). Runs 1B models on consumer CPUs at 50+ tok/s using <700MB RAM. No h…☆21Jun 2, 2026Updated 4 months ago
- ☆15Mar 22, 2024Updated 2 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- A Verilog implementation of a hand-written digit recognition Neural Network☆11Nov 16, 2024Updated last year
- A collection of Beamer samples in Persian☆16May 7, 2024Updated 2 years ago
- ☆29Updated this week
- Production-ready ternary quantized (1.58-bit) Rust code generation model with mHC-lite, MaxRL training, and comprehensive benchmarking☆22Aug 2, 2026Updated 2 months ago
- ☆15Mar 5, 2025Updated last year
- A desktop VRM character (小光) that gives your AI agent a face — chats, speaks, listens, lip-syncs, and emotes on macOS.☆28Jul 19, 2026Updated 3 months ago
- High-level synthesis (HLS) implementation of Sparse Matrix Vector Multiplication☆20Feb 17, 2022Updated 4 years ago
- A tiny Verilog CNN accelerator for the Tang Nano 20K. Features INT8 quantized weights, a streaming MAC array, and full on-chip MNIST infe…☆17May 26, 2026Updated 4 months ago
- A do-it-all container node for Godot☆10Aug 12, 2023Updated 3 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Implementation for IceFormer: Accelerated Inference with Long-Sequence Transformers on CPUs (ICLR 2024).☆25Jun 9, 2026Updated 4 months ago
- A generic genetic programming framework that aims to make genetic programming easier for a myriad of uses. Currently, the main target is …☆26Jun 9, 2022Updated 4 years ago
- Get list of all NordVPN active servers☆25Aug 9, 2017Updated 9 years ago
- ☆15Aug 2, 2025Updated last year
- Inference Llama/Llama2/Llama3 Modes in NumPy☆21Nov 22, 2023Updated 2 years ago
- 不定期更新☆150Sep 28, 2026Updated 3 weeks ago
- Hardware and Software Co-design implementations☆16Dec 5, 2019Updated 6 years ago
- A minimalistic SOCKS5 proxy over a network interface (like a VPN or a second physical network device)☆37Apr 19, 2026Updated 6 months ago
- Experimental deltachat client☆15May 11, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board.☆16Aug 7, 2022Updated 4 years ago
- To take down the code that I've written in course.☆12Jun 23, 2024Updated 2 years ago
- Parallel Genetic Algorithm Library originally by David Levine from Argonne National Laboratory