gergo- / ldrgen
Liveness-driven random C code generator
☆40Updated 2 months ago
Related projects: ⓘ
- Source code for the equivalence checker presented in the PLDI 2019 paper, "Semantic Program Alignment for Equivalence Checking"☆36Updated 4 years ago
- Automatic Binary Parallelisation☆36Updated 11 months ago
- Visualization of LLVM IR☆60Updated 10 years ago
- A toy code generator (i.e. "program synthesis") using the Z3 solver☆32Updated 6 years ago
- SMT solver for the theory of floating-point arithmetic☆26Updated 6 years ago
- Parser for the llvm bitcode format☆59Updated 2 weeks ago
- CCG is a random C Code Generator☆43Updated 2 years ago
- Verifying x86 semantics☆10Updated 7 years ago
- Example implementation of Arm's Architecture Specification Language (ASL)☆34Updated 2 years ago
- Example implementation of Arm's Architecture Specification Language (ASL)☆107Updated 5 years ago
- Automatic inference of a formal specification of the x86_64 instruction set☆65Updated 8 years ago
- print information from LLVM dataflow analyses☆13Updated 4 years ago
- A benchmark for C program verification☆15Updated 6 months ago
- llvm opt fuzzer and bounded exhaustive test generator☆38Updated last year
- A (concrete or symbolic) implementation of IEEE-754 / SMT-LIB floating-point☆38Updated 2 years ago
- Verified, Incremental, Binary Editing with Synthesis☆46Updated last year
- A library for binary analysis and rewriting☆47Updated 11 months ago
- AST - Extractor for LLVM☆17Updated 3 years ago
- Experimental translation of llvm to smt.☆57Updated 4 years ago
- A tool for testing C compilers automatically☆20Updated 8 years ago
- ☆48Updated 8 years ago
- Sail version of Arm ISA definition, currently for Armv9.3-A, and with the previous Sail Armv8.5-A model☆70Updated 3 weeks ago
- Generates CIL MLIR dialect from C/C++ source.☆31Updated 3 years ago
- ☆24Updated 3 months ago
- Partial Redundancy Elimination Pass in LLVM☆12Updated 5 years ago
- Linux kernel library functions formally verified.☆48Updated 3 years ago
- OCaml library to transform an Llvm control flow graph in an SMT formula.☆13Updated 6 years ago
- Program synthesis tools and utilities for LLVM.☆20Updated last year
- A collection of slides of the SMT course I held at University of Milan in fall 2011☆7Updated 9 years ago
- Counter-example guided inductive synthesis (CEGIS) implementation for the SMT solver Z3 by Microsoft Research☆44Updated 7 years ago